DMA Accelerator Functional Unit User Guide: Intel® FPGA Programmable Acceleration Card D5005

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ID 683270
Date 8/03/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the DMA AFU Example 7. Simulating the AFU Example 8. Optimization for Improved DMA Performance 9. DMA Accelerator Functional Unit User Guide Archives 10. Document Revision History for the DMA Accelerator Functional Unit User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space 3.1.2. Device Feature Header Linked-List
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the DMA AFU Example
7. Simulating the AFU Example
8. Optimization for Improved DMA Performance
9. DMA Accelerator Functional Unit User Guide Archives
10. Document Revision History for the DMA Accelerator Functional Unit User Guide

4. Software Programming Model

The DMA AFU includes a software driver that you can use in your own host application. The fpga_dma.cpp and fpga_dma.h files located at the following location implement the software driver: 
$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw

This driver supports the following functions:
API Description
fpgaCountDMAChannels

Scans the device feature chain for DMA BBBs and count all available channels.

fpgaDMAOpen Opens a handle to the DMA channel.
fpgaDMAClose Closes a handle to the DMA channel.
fpgaDMATransferInit Initializes an object that represents the DMA transfer.
fpgaDMATransferReset Resets the DMA transfer attribute object to default values.
fpgaDMATransferDestroy Destroys the DMA transfer attribute object.
fpgaDMATransferSetSrc Sets the source address of the transfer. This address must be 64 byte aligned.
fpgaDMATransferSetDst Sets the destination address of the transfer. This address must be 64 byte aligned.
fpgaDMATransferSetLen Sets the transfer lengths in bytes. For non-packet transfers, you must set the transfer length to a multiple of 64 bytes. For packet transfers, this is not a requirement.
fpgaDMATransferSetTransferType Sets the transfer type.
Legal values are:
  • HOST_MM_TO_FPGA_MM = TX (Host to AFU)
  • FPGA_MM_TO_HOST_MM = RX (AFU to host)
fpgaDMATransferSetTransferCallback Registers callback for notification on asynchronous transfer completion. If you specify a callback, fpgaDMATransfer returns immediately (asynchronous transfer).

If you do not specify a callback, fpgaDMATransfer returns after the transfer is complete (synchronous/blocking transfer).

fpgaDMATransferSetLast Indicates the last transfer so the DMA can start processing the prefetched transfers. The default value is 64 transfers in the pipeline before the DMA starts to work on the transfers.
fpgaDMATransfer Performs a DMA transfer.

For more information about the API, input, and output arguments, refer to the header file located at $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw/fpga_dma.h

To know more about software driver use model, refer to the README file located at $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/README.md

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