Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

ID 683247
Date 11/07/2023
Document Table of Contents

2.10. Block-Based Design Flows Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.11.07 23.3
  • Added Top FAQs navigation to the document cover.
  • Removed references to design block preservation as new DNI infrastructure does not support the "preserve" assignment.
2019.12.16 19.4.0
  • Updated for cross-device snapshot reuse support and limits throughout.
2019.11.11 19.2.0
  • Described Fast Preserve option in "Block-Based Design Terminology" and "Step 4: Add the Root Partition and Compile."
2019.07.15 19.2.0
  • Changed default file export location from output_files to project directory.
  • Updated description of partition type GUI.
  • Updated Support for "Combined Incremental Block-Based Compilation and Design Block Reuse" table for latest supported combinations.
  • Added note about merging partitions to "Creating Design Partitions."
2018.10.01 18.1.0
  • Removed reference to Placed snapshot from "Step 3: Compile and Export the Root Partition." Only Synthesized and Final snapshots are supported for design block reuse.
2018.09.24 18.1.0
  • Reorganized order of topics in chapter.
  • Added the following new topics:
    • Viewing Quartus Database File Information
    • Reserved Core Entity Re-Binding
    • Incremental Block-Based Compilation Examples
    • Design Methodologies
    • Top-Down Design Methodology Overview
    • Bottom-Up Design Methodology Overview
    • Bottom-Up Design Recommendations and Limitations
    • Team-Based Design Methodology Overview
    • Incremental Timing Closure
    • Incremental Timing Closure Recommendations and Limitations
    • Design Abstraction
  • Replaced references to "periphery reuse core" with "reserved core" to reflect latest GUI.
  • Added description of | as root partition hierarchy path in Design Partitions Window.
  • Replaced details in "Debugging Block-Based Designs with the Signal Tap Logic Analyzer" section with link to AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board.
  • Minor wording and graphic updates throughout.
  • Removed references to unsupported Planned snapshot.
2018.05.07 18.0.0
  • First release of chapter as part of stand-alone Block-Based Design User Guide.
  • Added footnote and links to known issues.
  • Updated all design flow steps to match current GUI.
  • Updated description of Include entity-bound SDC files option.
  • Updated statement defining parent to child partition attribute inheritance.
  • Added Design Partition Settings topic.
  • Added Block-Based Design Terminology topic.
  • Added Preservation and Reuse with Compiler Snapshots topic.
  • Added Empty Partition Clock Source Preservation topic.
  • Added Design Partitions Properties table.
  • Added Combining Incremental Block-Based Compilation and Design Block Reuse topic.
  • Updated Debugging Block-Based Designs topic and linked to new Application Note.
2017.11.06 17.1.0
  • Reorganization of introduction and Incremental Block-Based Compilation.
  • Added Design Partitioning section.
  • Added Debugging Block-Based Designs section.
  • Added Use Empty Partitions to Reduce Compilation Time topic.
  • Removed requirement to add .psmf, .msf, and .sof to Consumer project.
  • Added Intel® Stratix® 10 support, including information about bundling of .sdc with exported partitions for Intel® Stratix® 10 designs.
  • Documented changes to Design Partitions window, Export Design Partition dialog box, and Logic Lock Regions window.
  • Added reference to new Design Partition Planner.
  • Updated references to corresponding .qsf assignments.
  • Changed references from periphery reuse to root partition reuse.
  • Rebranded for latest Intel® standards.
2017.05.08 17.0.0
  • First public release.