Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 12/02/2022
Public

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4.3.11.2. User Configurable Timing Constraint

DCFIFO contains multi-bit gray-coded asynchronous clock domain crossing (CDC) paths which derives the DCFIFO fill-level. In order for the logic to work correctly, the value of the multi-bit must always be sampled as 1-bit change at a given latching clock edge.

In the physical world, flip-flops do not have the same data and clock path insertion delays. It is important for you to ensure and check the 1-bit change property is properly set. You can confirm this using the Fitter and check using the Timing Analyzer.

Timing Analyzer applies the following timing constraints for DCFIFO:

  • Paths crossing from write into read domain are defined from the delayed_wrptr_g to rs_dgwp registers.
    • set from_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|delayed_wrptr_g*]
    • set to_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*]
  • Paths crossing from read into write domain are defined from the rdptr_g and ws_dgrp registers.
    • set from_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|*rdptr_g*]
    • set to_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*]
  • For the above paths which cross between write and read domain, the following assignments apply:
    • set_max_skew -from $from_node_list -to $to_node_list
      -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.8
    • set_min_delay -from $from_node_list -to $to_node_list -100
    • set_max_delay -from $from_node_list -to $to_node_list 100
    • set_net_delay -from $from_node_list -to $to_node_list -max
      -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
  • The following set_net_delay on cross clock domain nets are for metastability:.
    • set from_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*]
      set to_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*] 
    • set from_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*]
      set to_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*]
    • set_net_delay -from $from_node_list -to $to_node_list -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8

Timing Analyzer applies the following timing constraints for mix-width DCFIFO:

  • Paths crossing from write into read domain are defined from the delayed_wrptr_g to rs_dgwp registers.
    • set from_node_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g*]
      
    • set to_node_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe*|dffe*]
  • Paths crossing from read into write domain are defined from the rdptr_g and ws_dgrp registers.
    • set from_node_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|*rdptr_g*]
    • set to_node_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe*|dffe*]
  • For the above paths which cross between write and read domain, the following assignments apply:
    • set_max_skew -from $from_node_list -to $to_node_list -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.8
    • set_min_delay -from $from_node_list -to $to_node_list -100
    • set_max_delay -from $from_node_list -to $to_node_list 100
    • set_net_delay -from $from_node_list -to $to_node_list -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
  • The following set_net_delay on cross clock domain nets are for metastability:
    • set from_node_mstable_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe*|dffe*]
      set to_node_mstable_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe*|dffe*] 
    • set from_node_mstable_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe*|dffe*]
      set to_node_mstable_list [get_keepers $hier_path|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe*|dffe*]
    • set_net_delay -from $from_node_list -to $to_node_list -max - get_value_from_clock_period dst_clock_period -value_multiplier 0.8