Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 12/02/2022

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4.4.5. Shift Register Ports and Parameters Setting

The following figure below shows the ports and parameters for the Shift Register (RAM-based) Intel® FPGA IP.

The parameter details are only relevant when implementing the IP directly in HDL.
Figure 49. Shift Register (RAM-based) Intel® FPGA IP Ports and Parameters
Table 57.  Shift Register (RAM-based) Intel® FPGA IP Input Ports
Name Required Description
shiftin[] Yes Data input to the shifter. Input port WIDTH bits wide.
clock Yes Positive-edge triggered clock.
clken No Clock enable for the clock port. clken defaults to VCC.
aclr No Asynchronously clears the contents of the shift register chain. The shiftout outputs are cleared immediately upon the assertion of the aclr signal.
sclr No Synchronously clears the registered output ports. The shiftout outputs are cleared upon the assertion of the sclr signal at positive clock edge.
Table 58.  Shift Register (RAM-based) Intel® FPGA IP Output Ports
Name Required Description
shiftout[] Yes Output from the end of the shift register. Output port WIDTH bits wide.
taps[] Yes Output from the regularly spaced taps along the shift register. Output port WIDTH * NUMBER_OF_TAPS wide. This port is an aggregate of all the regularly spaced taps (each WIDTH bits) along the shift register.
Table 59.  Shift Register (RAM-based) Intel® FPGA IP Parameters
Name Type Required Description
NUMBER_OF_TAPS Integer Yes Specifies the number of regularly spaced taps along the shift register.
TAP_DISTANCE Integer Yes Specifies the distance between the regularly spaced taps in clock cycles. This number translates to the number of RAM words that is used. TAP_DISTANCE must be at least 3.
WIDTH Integer Yes Specifies the width of the input pattern.
POWER_UP_STATE String No Specifies the shift register contents at power-up. Values are CLEARED and DONT_CARE. If omitted, the default is CLEARED.
Value Description
CLEARED Zero content.
DONT_CARE Unknown content. M-RAM blocks can be used with this setting.