Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 12/02/2022

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4.2.4. eSRAM Intel® Agilex™ FPGA IP Interface Signals

The following table lists the input and output signals of the eSRAM Intel® Agilex™ FPGA IP interface.
Table 35.  eSRAM Intel® Agilex™ FPGA IP Input and Output Signals
Signal Direction Width Description
clock Input 1 Provide a reference clock.
p<port_number>_data Input Range from


1 to 64 bits.
p<port_number>_rdaddress Input Range from


Read address if the memory. Dependent on how many banks are enabled in the channel.
Note: If you attempt to read from an invalid address, the data returned is random and of no value.
p<port_number>_rden Input 1 Active high read enable input for the rdaddress port.
p<port_number>_sd Input 1 Active high signal that dynamically shuts down ports. This signal shuts down power to periphery and memory core of the banks within the port, with no memory data retention. In addition to the channels that are statically shut down when choosing the number of channels to use in an eSRAM system, you can also dynamically shut down ports at run time.
Note: Memory contents are not retained when a port is shut down.
p<port_number>_wraddress Input Range from


Write address of the memory. Dependent on how many banks are enabled in the port.
Note: Writing to an invalid address does nothing, because the targeted bank is not powered.
p<port_number>_wren Input 1 Active high write enable input for the wraddress port.
p<port_number>_q Output Range from


1 to 64 bits.
p<port_number>_eccflags Output 2 p<port_number>_eccflags[0] represents error detect, asserts when an ECC error occurred on the read data retrieved from the eSRAM. p<port_number>_eccflags[1] represents error correct, asserts when an ECC error is successfully corrected and the memory content is not updated with the corrected data.