MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 8/20/2024
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Device Family Pin Connection Guidelines x
MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for MAX® 10 FPGA Devices Document Revision History for the MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins MAX® 10 (Single Supply) FPGA MAX® 10 (Dual Supply) FPGA Notes to the MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for MAX® 10 FPGA Devices x
Example 1— MAX® 10 (Dual Supply) FPGA Example 2— MAX® 10 (Dual Supply) FPGA Example 3— MAX® 10 (Dual Supply) FPGA Example 4— MAX® 10 (Single Supply) FPGA Example 5— MAX® 10 (Single Supply) FPGA Example 6— MAX® 10 (Single Supply) FPGA
MAX® 10 FPGA Device Family Pin Connection Guidelines

Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Document Version Changes
2022.05.27 Removed all instances of Enpirion from Example 1—Intel MAX 10 (Dual Supply) FPGA, Example 2—Intel MAX 10 (Dual Supply) FPGA, Example 3—Intel MAX 10 (Dual Supply) FPGA, Example 4—Intel MAX 10 (Single Supply) FPGA, Example 5—Intel MAX 10 (Single Supply) FPGA and Example 6—Intel MAX 10 (Single Supply) FPGA sections.
2022.04.27 Updated the pin description of the ADC[1..2]IN[1..16] pins.
2021.11.26 Updated the connection guidelines of the VCCIO[#] pins for the Intel® MAX® 10 (Single Supply) FPGA and Intel® MAX® 10 (Dual Supply) FPGA.
2021.11.01
  • Updated the 1.0-V VCCIO note in the connection guidelines of the VCCIO[#] pins in the Intel® MAX® 10 (Single Supply) FPGA and Intel® MAX® 10 (Dual Supply) FPGA.
2020.06.30
  • Added the 1.0-V support to the VCCIO[#] pins for the Intel® MAX® 10 (Single Supply) FPGA and Intel® MAX® 10 (Dual Supply) FPGA.
  • Added 1.0-V support to the VCCIO power supplies in the following power supply sharing guidelines:
    • Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Dual Supply) FPGA – The ADC Feature is Not Used
    • Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 1.0V/1.2V/1.35V/1.5V/1.8V/2.5V/3.0V/3.3V
    • Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Single Supply) FPGA (E144, M153, U169, and U324 Packages) – The ADC Feature is Not Used
    • Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.0V/1.2V/1.35V/1.5V/1.8V/2.5V (E144, M153, U169, and U324 Packages)
2019.07.01
  • Updated the connection guidelines about how to enable the ADC feature in the VCCIO[#] pin of the Intel® MAX® 10 (Single Supply) FPGA table.
  • Updated the connection guidelines of the DEV_CLRn and DEV_OE pins.
2019.02.20 Updated the connection guidelines of the DEV_CLRn and DEV_OE pins.
2019.01.29
  • Updated the connection guidelines of the CONFIG_SEL pin.
  • Updated note 10 in the Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines section.
Date Version Description of Changes
December 2017 2017.12.15
  • Added the support for the U324 package.
  • Added a reference for the UFM and CFM power-down requirement to the VCCA[1..6] pins for the Intel® MAX® 10 (Single Supply) FPGA and VCCA[1..4] pins for the Intel® MAX® 10 (Dual Supply) FPGA.
  • Added a note to provide references for each PLL clock output of the PLL_[L,R,B,T]_CLKOUTp and PLL_[L,R,B,T]_CLKOUTn pins.
  • Updated the voltage overshoot connection guidelines for the TCK, TDO, TDI, and TMS pins.
  • Updated the Voltage Sensor Pins section to Analog Input Pins.
  • Removed PowerPlay text from tool name.
June 2017 2017.06.16 Updated the connection guidelines of the JTAGEN pin.
February 2017 2017.02.21
  • Rebranded as Intel.
December 2016 2016.12.09
  • Updated the connection guidelines of the TDI and TMS pins.
May 2016 2016.05.02
  • Added note (5) to the following power sharing guidelines:
    • Example 1. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – The ADC Feature is Not Used
    • Example 2. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5V
    • Example 3. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 1.2V/1.35V/1.5V/1.8V/3.0V/3.3V
  • Added note (4) to the following power sharing guidelines:
    • Example 4. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA (E144, M153, and U169 Packages) – The ADC Feature is Not Used
    • Example 5. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V
    • Example 6. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.2V/1.35V/1.5V/1.8V/2.5V
  • Updated CONF_DONE should pulled up to VCCIO Bank 8.
  • Removed Note 3 “The voltage level for each power rail is preliminary.” from the following power sharing guidelines:
    • Example 1. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – The ADC Feature is Not Used
    • Example 2. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5V
    • Example 3. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 1.2V/1.35V/1.5V/1.8V/3.0V/3.3V
    • Example 4. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA (E144, M153, and U169 Packages) – The ADC Feature is Not Used
    • Example 5. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V (E144, M153, and U169 Packages)
    • Example 6. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.2V/1.35V/1.5V/1.8V/2.5V (E144, M153, and U169 Packages)
November 2015 2015.11.02
  • Changed instances of Quartus II to Quartus Prime.
  • Updated the connection guidelines of the VCCIO[#] pins.
  • Updated the connection guidelines of the TDI and TMS pins.
June 2015 2015.06.12 Added the DNU pin.
May 2015 2015.05.06
  • Added the following power sharing guidelines:
    • Example 2. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5V
    • Example 3. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 1.2V/1.35V/1.5V/1.8V/3.0V/3.3V
    • Example 5. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V (E144, M153, and U169 Packages)
    • Example 6. Power Supply Sharing Guidelines for MAX 10S (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.2V/1.35V/1.5V/1.8V/2.5V (E144, M153, and U169 Packages)
  • Updated the following power sharing guidelines:
    • Example 1. Power Supply Sharing Guidelines for MAX 10D (Dual Supply) FPGA – The ADC Feature is Not Used
  • Updated the pin description of the DPCLK[0..3] pins.
  • Updated the connection guidelines of the VCCIO[#] pins.
  • Updated the connection guidelines of the ADC[1..2]IN[1..16] pins.
  • Updated the connection guidelines of the ADC_VREF pin.
January 2015 2015.01.29
  • Updated the connection guidelines of the DPCLK[0..3] pins.
  • Updated the connection guidelines of the PLL_[L,R,B,T]_CLKOUTp and PLL_[L,R,B,T]_CLKOUTn pins.
  • Updated the connection guidelines of the VREFB<#>N0 pins.
  • Updated the pin description of the ADC[1..2]IN[1..16] pins.
December 2014 2014.12.15
  • Added note 10 in the Notes to Pin Connection Guidelines.
  • Added note (**) to Figure 2.
  • Updated the pin name from BOOT_SEL to CONFIG_SEL.
  • Updated the pin description of the CONFIG_SEL pin.
  • Updated the connection guidelines of the VCC_ONE pin.
  • Updated the connection guidelines of the nSTATUs pin.
  • Updated the connection guidelines of the CONF_DONE pin.
  • Updated note 4 in the Notes to Pin Connection Guidelines.
September 2014 2014.09.22 Initial release.
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