Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide
ID
683221
Date
11/10/2022
Public
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. TX PCS Interface to User Logic
6.4. RX PCS Interface to User Logic
6.5. Transceivers Signals
6.6. Transceiver Reconfiguration Signals
6.7. Avalon® Memory-Mapped Management Interface
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
6.10. Clocks
6.11. Flow Control Interface
4.2. User Interface to Ethernet Transmission
The IP core reverses the bit stream for transmission per Ethernet requirements. The transmitter handles the insertion of the inter-packet gap, frame delimiters, and padding with zeros as necessary. The transmitter also handles FCS computation and insertion.
The IP core transmits complete packets. After transmission begins, it must complete with no IDLE insertions. Between the end of one packet and the beginning of the next packet, the data input is not considered and the transmitter sends IDLE characters. An unbounded number of IDLE characters can be sent between packets.