Triple-Speed Ethernet IP Release Notes

Download PDF
ID 683215
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Triple-Speed Ethernet IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet IP (intel_eth_tse) v9.0.0 1.2. Triple-Speed Ethernet IP (intel_eth_tse) v8.0.0 1.3. Triple-Speed Ethernet IP (intel_eth_tse) v7.0.0 1.4. Triple-Speed Ethernet IP (intel_eth_tse) v6.0.0 1.5. Triple-Speed Ethernet IP (intel_eth_tse) v5.0.0 1.6. Triple-Speed Ethernet IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet (altera_eth_tse) IP v23.0.0 2.2. Triple-Speed Ethernet (altera_eth_tse) IP v22.6.0 2.3. Triple-Speed Ethernet (altera_eth_tse) IP v22.5.0 2.4. Triple-Speed Ethernet (altera_eth_tse) IP v22.4.0 2.5. Triple-Speed Ethernet IP (altera_eth_tse) v22.3.0 2.6. Triple-Speed Ethernet (altera_eth_tse) v22.2.0 2.7. Triple-Speed Ethernet IP v22.1.0 2.8. Triple-Speed Ethernet IP v22.0.0 2.9. Triple-Speed Ethernet IP v21.2.0 2.10. Triple-Speed Ethernet IP v21.1.0 2.11. Triple-Speed Ethernet IP v20.0.0 2.12. Triple-Speed Ethernet IP v19.5.0 2.13. Triple-Speed Ethernet IP v19.4.0 2.14. Triple-Speed Ethernet IP v19.2.0 2.15. Triple-Speed Ethernet IP v19.1 2.16. Triple-Speed Ethernet IP v18.0 2.17. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.18. Triple Speed Ethernet IP Core v15.1 2.19. Triple Speed Ethernet IP Core v15.0 2.20. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.21. Triple Speed Ethernet IP Core v14.0 2.22. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.23. Triple Speed Ethernet IP Core v13.1 2.24. Triple-Speed Ethernet IP User Guide Archives 2.25. Triple-Speed Ethernet Stratix® 10 IP Design Example User Guide Archives
1. Triple-Speed Ethernet IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet IP (altera_eth_tse) Release Notes

1.1. Triple-Speed Ethernet IP (intel_eth_tse) v9.0.0

Table 1.  v9.0.0 2025.08.04
Quartus® Prime Version Description Impact
25.1.1
  • Added support for IEEE 1588v2 Precision Time Protocol for Agilex™ 3 and Agilex™ 5 devices.
  • Added the following design examples for Agilex™ 5 devices:
    • 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2
    • 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2
  • Enabled LVDS Pin Settings in the IP parameter editor for Agilex™ 3 and Agilex™ 5 devices.
  • Improved simulation model which allows faster simulation time for all simulators.
 —
Level Two Title