1.16. Triple Speed Ethernet IP Core v13.1
|Removed support for the following devices:
|Added 1588v2 support for Arria V, Arria V SoC, Cyclone V, Cyclone V SoC and Stratix V devices.||-|
|Added 1588v2 support for MAC-only variants||-|
|Added ATX and CMU Tx PLL options for variations that include the PCS block targeting Arria V GZ and Stratix V devices.||-|
|Added SyncE support by separating Tx PLL and Rx PLL reference clock.||-|
|The period in nanosecond for csr registers: tx_period, rx_period, Period, and AdjustPeriod, was changed from bit 16 to 19 to bit 16 to 24.||-|
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