Triple-Speed Ethernet Intel® FPGA IP Release Notes

ID 683215
Date 4/01/2024
Document Table of Contents

2.17. Triple Speed Ethernet IP Core v13.1

Table 23.  v13.1 November 2013
Description Impact
Removed support for the following devices:
  • Arria GX
  • Cyclone II
  • HardCopy II, HardCopy III, and HardCopy IV
  • Stratix II and Stratix II GX
Added 1588v2 support for Arria V, Arria V SoC, Cyclone V, Cyclone V SoC and Stratix V devices. -
Added 1588v2 support for MAC-only variants -
Added ATX and CMU Tx PLL options for variations that include the PCS block targeting Arria V GZ and Stratix V devices. -
Added SyncE support by separating Tx PLL and Rx PLL reference clock. -
The period in nanosecond for csr registers: tx_period, rx_period, Period, and AdjustPeriod, was changed from bit 16 to 19 to bit 16 to 24. -