Triple-Speed Ethernet Intel® FPGA IP Release Notes

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ID 683215
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v6.0.0 1.2. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v5.0.0 1.3. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet (altera_eth_tse) Intel® FPGA IP v22.4.0 2.2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) v22.3.0 2.3. Triple-Speed Ethernet (altera_eth_tse) v22.2.0 2.4. Triple-Speed Ethernet Intel® FPGA IP v22.1.0 2.5. Triple-Speed Ethernet Intel® FPGA IP v22.0.0 2.6. Triple-Speed Ethernet Intel® FPGA IP v21.2.0 2.7. Triple-Speed Ethernet Intel® FPGA IP v21.1.0 2.8. Triple-Speed Ethernet Intel® FPGA IP v20.0.0 2.9. Triple-Speed Ethernet Intel® FPGA IP v19.5.0 2.10. Triple-Speed Ethernet Intel® FPGA IP v19.4.0 2.11. Triple-Speed Ethernet Intel® FPGA IP v19.2.0 2.12. Triple-Speed Ethernet Intel® FPGA IP v19.1 2.13. Triple-Speed Ethernet Intel® FPGA IP v18.0 2.14. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.15. Triple Speed Ethernet IP Core v15.1 2.16. Triple Speed Ethernet IP Core v15.0 2.17. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.18. Triple Speed Ethernet IP Core v14.0 2.19. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.20. Triple Speed Ethernet IP Core v13.1 2.21. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 2.22. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes

1.2. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v5.0.0

Table 2.  v5.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2
  • Added support for Agilex™ 5 D-Series FPGAs and SoCs.1
  • Added the following support for Agilex™ 5 devices:
    • Added hardware support for the 10/100/1000 ethernet MAC design example with 1000BASE-X/SGMII 2XTBI PCS with GTS transceiver.
    • Added support for analog parameter.
    • Removed VCS* simulator support.
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Related Information
1 Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.
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