Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
ID
813899
Date
7/08/2024
Public
1. Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 24.2 |
| IP Version 5.0.0 |
The Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 provides the capability of generating design examples for selected configurations, which allows you to:
- Compile the design to get an estimate of the IP area usage and timing.
- Simulate the design to verify the IP functionality through simulation.
- Test the design on the hardware using the Agilex™ 5 FPGA I-Series Transceiver-SoC Development Kit.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages for the Design Example
Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.