Triple-Speed Ethernet Intel® FPGA IP Release Notes

ID 683215
Date 7/08/2024
Public
Document Table of Contents

2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1

Table 18.  v17.1 November 2017
Description Impact

Added support for the Stratix® 10, Cyclone® 10 GX, and Cyclone® 10 LP device families.

These devices are only available in Quartus® Prime Pro Edition software version 17.1 onwards.
In versions 17.0.2 and earlier of the Triple-Speed Ethernet IP core, the Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Arria® 10 devices may experience performance risk. This issue is fixed in the Quartus® Prime software version 17.1. To upgrade designs from previous versions of the Quartus® Prime software to version 17.1, you must regenerate the Triple-Speed Ethernet IP core and recompile the design in the Quartus® Prime software version 17.1. Refer to the KDB page for more information.
The number of ports supported for Triple-Speed Ethernet design with LVDS I/O targeting Stratix® 10, Arria® 10, and Cyclone® 10 GX is 8 per instance. You must not promote the reference clock to global clock manually. Assign the number of ports supported and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed.
RGMII interface is not supported in Stratix® 10, Arria® 10, and Cyclone® 10 GX devices.