Triple-Speed Ethernet Intel® FPGA IP Release Notes

ID 683215
Date 12/19/2022
Public

1.8. Intel FPGA Triple Speed Ethernet IP Core v17.1

Table 12.  v17.1 November 2017
Description Impact

Added support for the Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Cyclone® 10 LP device families.

These devices are only available in Intel® Quartus® Prime Pro Edition software version 17.1 onwards.
In versions 17.0.2 and earlier of the Triple-Speed Ethernet IP core, the Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel® Arria® 10 devices may experience performance risk. This issue is fixed in the Intel® Quartus® Prime software version 17.1. To upgrade designs from previous versions of the Intel® Quartus® Prime software to version 17.1, you must regenerate the Triple-Speed Ethernet IP core and recompile the design in the Intel® Quartus® Prime software version 17.1. Refer to the KDB page for more information.
The number of ports supported for Triple-Speed Ethernet design with LVDS I/O targeting Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX is 8 per instance. You must not promote the reference clock to global clock manually. Assign the number of ports supported and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed.
RGMII interface is not supported in Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.

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