Triple-Speed Ethernet Intel® FPGA IP Release Notes

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ID 683215
Date 10/19/2023
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1. Triple-Speed Ethernet Intel® FPGA IP Release Notes
1. Triple-Speed Ethernet Intel® FPGA IP Release Notes x
1.1. Triple-Speed Ethernet Intel® FPGA IP v22.1.0 1.2. Triple-Speed Ethernet Intel® FPGA IP v22.0.0 1.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0 1.4. Triple-Speed Ethernet Intel® FPGA IP v21.1.0 1.5. Triple-Speed Ethernet Intel® FPGA IP v20.0.0 1.6. Triple-Speed Ethernet Intel® FPGA IP v19.5.0 1.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0 1.8. Triple-Speed Ethernet Intel® FPGA IP v19.2.0 1.9. Triple-Speed Ethernet Intel® FPGA IP v19.1 1.10. Triple-Speed Ethernet Intel® FPGA IP v18.0 1.11. Intel FPGA Triple Speed Ethernet IP Core v17.1 1.12. Triple Speed Ethernet IP Core v15.1 1.13. Triple Speed Ethernet IP Core v15.0 1.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 1.15. Triple Speed Ethernet IP Core v14.0 1.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 1.17. Triple Speed Ethernet IP Core v13.1 1.18. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 1.19. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet Intel® FPGA IP Release Notes

1.11. Intel FPGA Triple Speed Ethernet IP Core v17.1

Table 15.  v17.1 November 2017
Description Impact

Added support for the Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Cyclone® 10 LP device families.

These devices are only available in Intel® Quartus® Prime Pro Edition software version 17.1 onwards.
In versions 17.0.2 and earlier of the Triple-Speed Ethernet IP core, the Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel® Arria® 10 devices may experience performance risk. This issue is fixed in the Intel® Quartus® Prime software version 17.1. To upgrade designs from previous versions of the Intel® Quartus® Prime software to version 17.1, you must regenerate the Triple-Speed Ethernet IP core and recompile the design in the Intel® Quartus® Prime software version 17.1. Refer to the KDB page for more information.
The number of ports supported for Triple-Speed Ethernet design with LVDS I/O targeting Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX is 8 per instance. You must not promote the reference clock to global clock manually. Assign the number of ports supported and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed. —
RGMII interface is not supported in Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices. —
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