Triple-Speed Ethernet IP Release Notes

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ID 683215
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Triple-Speed Ethernet IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet IP (intel_eth_tse) v10.0.0 1.2. Triple-Speed Ethernet IP (intel_eth_tse) v9.0.0 1.3. Triple-Speed Ethernet IP (intel_eth_tse) v8.0.0 1.4. Triple-Speed Ethernet IP (intel_eth_tse) v7.0.0 1.5. Triple-Speed Ethernet IP (intel_eth_tse) v6.0.0 1.6. Triple-Speed Ethernet IP (intel_eth_tse) v5.0.0 1.7. Triple-Speed Ethernet IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet (altera_eth_tse) IP v24.0.0 2.2. Triple-Speed Ethernet (altera_eth_tse) IP v23.0.0 2.3. Triple-Speed Ethernet (altera_eth_tse) IP v22.6.0 2.4. Triple-Speed Ethernet (altera_eth_tse) IP v22.5.0 2.5. Triple-Speed Ethernet (altera_eth_tse) IP v22.4.0 2.6. Triple-Speed Ethernet IP (altera_eth_tse) v22.3.0 2.7. Triple-Speed Ethernet (altera_eth_tse) v22.2.0 2.8. Triple-Speed Ethernet IP v22.1.0 2.9. Triple-Speed Ethernet IP v22.0.0 2.10. Triple-Speed Ethernet IP v21.2.0 2.11. Triple-Speed Ethernet IP v21.1.0 2.12. Triple-Speed Ethernet IP v20.0.0 2.13. Triple-Speed Ethernet IP v19.5.0 2.14. Triple-Speed Ethernet IP v19.4.0 2.15. Triple-Speed Ethernet IP v19.2.0 2.16. Triple-Speed Ethernet IP v19.1 2.17. Triple-Speed Ethernet IP v18.0 2.18. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.19. Triple Speed Ethernet IP Core v15.1 2.20. Triple Speed Ethernet IP Core v15.0 2.21. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.22. Triple Speed Ethernet IP Core v14.0 2.23. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.24. Triple Speed Ethernet IP Core v13.1 2.25. Triple-Speed Ethernet IP User Guide Archives 2.26. Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet IP (altera_eth_tse) Release Notes

1.1. Triple-Speed Ethernet IP (intel_eth_tse) v10.0.0

Table 1.  v10.0.0 2025.09.29
Quartus® Prime Version Description Impact
25.3
  • Added support for HVIO PLL for Agilex™ 5 devices.
  • Added Avalon Debug Endpoint on Avalon Interface option in the parameter editor.
  • Added support for a single channel design generation (Number of Ports = 1) for 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) variant.
  • Added support for latency values calculation for PCS-only variation used with HPS GMII Adapter and LVDS I/O transceiver.
  • Enabled serial internal loopback testing for 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS and GTS Transceiver variant.
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