A newer version of this document is available. Customers should click here to go to the newest version.
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. IP Catalog and Parameter Editor
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
2.4. Simulating Intel® FPGA IP Cores
2.5. Simulating the FIR II IP Core Testbench in MATLAB
2.6. DSP Builder for Intel® FPGAs Design Flow
4.1. FIR II IP Core Interpolation Filters
4.2. FIR Decimation Filters
4.3. FIR II IP Core Time-Division Multiplexing
4.4. FIR II IP Core Multichannel Operation
4.5. FIR II IP Core Multiple Coefficient Banks
4.6. FIR II IP Core Coefficient Reloading
4.7. Reconfigurable FIR Filters
4.8. FIR II IP Core Interfaces and Signals
3. FIR II IP Core Parameters
You define a FIR filter by its coefficients. You specify the filter settings and coefficient options in the parameter editor.
The FIR II IP core provides a default 37-tap coefficient set regardless of the configurations from filter settings. The scaled value and fixed point value are recalculated based on the coefficient bit width setting. The higher the coefficient bit width, the closer the fixed frequency response is to the intended original frequency response with the expense of higher resource usage.
You can load the coefficients from a file. For example, you can create the coefficients in another application such as MATLAB or a user-created program, save the coefficients to a file, and import them into the FIR II IP core.