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2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. IP Catalog and Parameter Editor
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
2.4. Simulating Intel® FPGA IP Cores
2.5. Simulating the FIR II IP Core Testbench in MATLAB
2.6. DSP Builder for Intel® FPGAs Design Flow
4.1. FIR II IP Core Interpolation Filters
4.2. FIR Decimation Filters
4.3. FIR II IP Core Time-Division Multiplexing
4.4. FIR II IP Core Multichannel Operation
4.5. FIR II IP Core Multiple Coefficient Banks
4.6. FIR II IP Core Coefficient Reloading
4.7. Reconfigurable FIR Filters
4.8. FIR II IP Core Interfaces and Signals
1.2. FIR II IP Core Features
- Exploiting maximal designs efficiency through hardware optimizations such as:
- Interpolation
- Decimation
- Symmetry
- Decimation half-band
- Time sharing
- Easy system integration using Avalon® Streaming (Avalon-ST) interfaces.
- Memory and multiplier trade-offs to balance the implementation between logic elements (LEs) and memory blocks (M512, M4K, M9K, M10K, M20K, or M144K).
- Support for run-time coefficient reloading capability and multiple coefficient banks.
- User-selectable output precision via truncation, saturation, and rounding.