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2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. IP Catalog and Parameter Editor
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
2.4. Simulating Intel® FPGA IP Cores
2.5. Simulating the FIR II IP Core Testbench in MATLAB
2.6. DSP Builder for Intel® FPGAs Design Flow
4.1. FIR II IP Core Interpolation Filters
4.2. FIR Decimation Filters
4.3. FIR II IP Core Time-Division Multiplexing
4.4. FIR II IP Core Multichannel Operation
4.5. FIR II IP Core Multiple Coefficient Banks
4.6. FIR II IP Core Coefficient Reloading
4.7. Reconfigurable FIR Filters
4.8. FIR II IP Core Interfaces and Signals
4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles
Sometimes invalid cycles are inserted between the input data. An example where the clock rate = 320, sample rate = 10, yields a TDM factor of 32, inputChannelNum = 15, and interpolation factor is 10. In this case, the TDM factor is greater than inputChannelNum. The optimization produces a filter with PhysChanIn = 1, ChansPerPhyIn = 15, PhysChanOut = 5, and ChansPerPhyOut = 3.
The input data format in this case is 32 cycles long, which comes from the TDM factor. The number of channels is 15, so the filter expects 15 valid cycles together in a block, followed by 17 invalid cycles. You can insert extra invalid cycles at the end, but they must not interrupt the packets of data after the process has started. If the input sample rate is less than the clock rate, the pattern is always the same: a repeating cycle, as long as the TDM factor, with the number of channels as the number of valid cycles required, and the remainder as invalid cycles.
Figure 25. Correct Input Format (15 valid cycles, 17 invalid cycles)
Figure 26. Incorrect Input Format (15 valid cycles, 0 invalid cycles)If the number of invalid cycles is less than 17, the output format is incorrect,
Figure 27. Correct Input Format (15 valid cycles, 20 invalid cycles)