Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

18.1.4. Interface Signals

Table 158.  Interface Signals
Signal Width Direction Description
Clock
clk 1 Input 25MHz maximum input clock.
Reset
reset_n 1 Input Asynchronous reset used to reset Quad SPI Controller
Avalon® -MM Agent Interface for CSR (avl_csr)
avl_csr_addr 3 Input Avalon® -MM address bus. The address bus is in word addressing.
avl_csr_read 1 Input Avalon® -MM read control to csr
avl_csr_write 1 Input Avalon® -MM write control to csr
avl_csr_waitrequest 1 Output Avalon® -MM waitrequest control from csr
avl_csr_wrdata 32 Input Avalon® -MM write data bus to csr
avl_csr_rddata 32 Output Avalon® -MM read data bus from csr
avl_csr_rddata_valid 1 Output Avalon® -MM read data valid which indicates that csr read data is available
Interrupt Signals
irq 1 Output Interrupt signal to determine if there is an illegal write or illegal erase
Avalon® -MM Agent Interface for Memory Access (avl_ mem)
avl_mem_addr * Input

Avalon® -MM address bus. The address bus is in word addressing. The width of the address will depends on the flash memory density minus 2.

If you are using Arria® 10, then the MSB bits will be used for chip select information. User is allowed to select the number of chip select needed in the GUI.

If user selects 1 chip select, there will be no extra bit added to avl_mem_addr.

If user select 2 chip selects, there will be one extra bit added to avl_mem_addr.

Chip 1 – b’0

Chip 2 – b’1

If user select 3 chip selects, there will be two extra bit added to avl_mem_addr.

Chip 1 – b’00

Chip 2 – b’01

Chip 3 – b’10

avl_mem_read 1 Input Avalon® -MM read control to memory
avl_mem_write 1 Input Avalon® -MM write control to memory
avl_mem_wrdata 32 Input Avalon® -MM write data bus to memory
avl_mem_byteenble 4 Input Avalon® -MM write data enable bit to memory. During bursting mode, byteenable bus bit will be all high always, 4’b1111.
avl_mem_burstcount 7 Input Avalon® -MM burst count for memory. Value range from 1 to 64
avl_mem_waitrequest 1 Output Avalon® -MM waitrequest control from memory
avl_mem_rddata 32 Output Avalon® -MM read data bus from memory
avl_mem_rddata_valid 1 Output Avalon® -MM read data valid which indicates that memory read data is available
Conduit Interface
flash_dataout 4 Input/Output Input/output port to feed data from flash device
flash_dclk_out 1 Output Provides clock signal to the flash device
flash_ncs 1/3 Output Provides the ncs signal to the flash device
The Intel FPGA Serial Flash Controller supports FMAX at 25 MHz.
Note: When using the Intel FPGA Serial Flash Controller Core with an external EPCQ flash, the interface mapping for control signal is not required.