Embedded Peripherals IP User Guide

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ID 683130
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Avalon® -ST Serial Peripheral Interface Core 3. SPI Core 4. SPI Agent/JTAG to Avalon® Host Bridge Cores 5. Intel eSPI Agent Core 6. eSPI to LPC Bridge Core 7. Ethernet MDIO Core 8. Intel FPGA 16550 Compatible UART Core 9. UART Core 10. Lightweight UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. EPCS/EPCQA Serial Flash Controller Core 17. Intel FPGA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller II Core 19. Intel FPGA Generic QUAD SPI Controller Core 20. Intel FPGA Generic QUAD SPI Controller II Core 21. Interval Timer Core 22. Intel FPGA Avalon FIFO Memory Core 23. On-Chip Memory (RAM and ROM) Intel FPGA IP 24. On-Chip Memory II (RAM or ROM) Intel FPGA IP 25. PIO Core 26. PLL Cores 27. DMA Controller Core 28. Modular Scatter-Gather DMA Core 29. Scatter-Gather DMA Controller Core 30. Video Sync Generator and Pixel Converter Cores 31. Intel FPGA Interrupt Latency Counter Core 32. Performance Counter Unit Core 33. Vectored Interrupt Controller Core 34. System ID Peripheral Core 35. Intel FPGA GMII to RGMII Converter Core 36. HPS GMII to RGMII Adapter IP 37. Intel FPGA MII to RMII Converter Core 38. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core IP 39. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 40. Intel FPGA MSI to GIC Generator Core 41. Cache Coherency Translator IP 42. Altera ACE5-Lite Cache Coherency Translator
1. Introduction x
1.1. Tool Support 1.2. Device Support 1.3. Driver Support 1.4. Embedded Peripherals IP User Guide Archives 1.5. Document Revision History for Embedded Peripherals IP User Guide
2. Avalon® -ST Serial Peripheral Interface Core x
2.1. Functional Description 2.2. Configuration 2.3. Avalon® -ST Serial Peripheral Interface Core Revision History
2.1. Functional Description x
2.1.1. Interfaces 2.1.2. Operation 2.1.3. Timing 2.1.4. Limitations
3. SPI Core x
3.1. Core Overview 3.2. Functional Description 3.3. Configuration 3.4. Software Programming Model 3.5. Example Test Code 3.6. SPI Core Revision History
3.2. Functional Description x
3.2.1. Example Configurations 3.2.2. Transmitter Logic 3.2.3. Receiver Logic 3.2.4. Host and Agent Modes
3.2.4. Host and Agent Modes x
3.2.4.1. Host Mode Operation 3.2.4.2. Agent Mode Operation 3.2.4.3. Multi-Agent Environments
3.3. Configuration x
3.3.1. Host/Agent Settings 3.3.2. Data Register Settings 3.3.3. Timing Settings 3.3.4. Synchronizer Stages
3.3.1. Host/Agent Settings x
3.3.1.1. Number of Select (SS_n) Signals 3.3.1.2. SPI Clock (sclk) Rate 3.3.1.3. Specify Delay
3.4. Software Programming Model x
3.4.1. Hardware Access Routines 3.4.2. Software Files 3.4.3. Register Map
3.4.1. Hardware Access Routines x
3.4.1.1. alt_avalon_spi_command()
3.4.3. Register Map x
3.4.3.1. rxdata Register 3.4.3.2. txdata Register 3.4.3.3. status Register 3.4.3.4. control Register 3.4.3.5. slaveselect Register 3.4.3.6. end of packet value Register
4. SPI Agent/JTAG to Avalon® Host Bridge Cores x
4.1. Core Overview 4.2. Functional Description 4.3. Parameters 4.4. SPI Agent/JTAG to Avalon® Host Bridge Cores Revision History
5. Intel eSPI Agent Core x
5.1. Functional Description 5.2. Resource Utilization 5.3. IP Parameters 5.4. Interface Signals 5.5. Registers 5.6. Peripheral Channel Avalon Interface Use Model 5.7. Intel eSPI Agent Core Revision History
5.1. Functional Description x
5.1.1. Link Layer 5.1.2. Transaction Layer 5.1.3. Channel Specific Layer 5.1.4. Port80 Implementation 5.1.5. VW message to Physical Port Implementation 5.1.6. Avalon® Memory-Mapped Interface Settings
5.1.3. Channel Specific Layer x
5.1.3.1. Peripheral Channel 5.1.3.2. Virtual Wire Channel
5.1.3.2. Virtual Wire Channel x
5.1.3.2.1. Interrupt Event
5.5. Registers x
5.5.1. Avalon® memory-mapped interface Accessible Registers 5.5.2. eSPI Interface Accessible Registers
5.5.1. Avalon® memory-mapped interface Accessible Registers x
5.5.1.1. Status Register 5.5.1.2. Control Register 5.5.1.3. Error Register
5.5.2. eSPI Interface Accessible Registers x
5.5.2.1. eSPI Status Register 5.5.2.2. Capabilities and Configuration Registers
6. eSPI to LPC Bridge Core x
6.1. Unsupported LPC Features 6.2. IP Parameters 6.3. Supported IP Clock Frequency 6.4. Functional Description 6.5. Interface Signals 6.6. Registers 6.7. eSPI to LPC Bridge Core Revision History
6.4. Functional Description x
6.4.1. FIFO Implementation 6.4.2. Transaction Ordering Rule 6.4.3. eSPI Command to LPC Cycle Type Conversion 6.4.4. SERIRQ Interrupt Event
6.6. Registers x
6.6.1. Status Register 6.6.2. Error Register
7. Ethernet MDIO Core x
7.1. Core Overview 7.2. Functional Description 7.3. Parameter 7.4. Configuration Registers 7.5. Interface Signals 7.6. Ethernet MDIO Core Revision History
7.2. Functional Description x
7.2.1. MDIO Frame Format (Clause 45) 7.2.2. MDIO Clock Generation 7.2.3. Interfaces 7.2.4. Operation
7.2.4. Operation x
7.2.4.1. Write Operation 7.2.4.2. Read Operation
8. Intel FPGA 16550 Compatible UART Core x
8.1. Core Overview 8.2. Feature Description 8.3. Software Programming Model 8.4. Address Map and Register Descriptions 8.5. Intel FPGA 16550 Compatible UART Core Revision History
8.2. Feature Description x
8.2.1. Unsupported Features 8.2.2. Interface 8.2.3. General Architecture 8.2.4. 16550 UART General Programming Flow Chart 8.2.5. Configuration Parameters 8.2.6. DMA Support 8.2.7. FPGA Resource Usage 8.2.8. Timing and Fmax 8.2.9. Avalon® -MM Agent 8.2.10. Over-run/Under-run Conditions 8.2.11. Hardware Auto Flow-Control 8.2.12. Clock and Baud Rate Selection
8.2.9. Avalon® -MM Agent x
8.2.9.1. Read behavior 8.2.9.2. Write behavior
8.2.10. Over-run/Under-run Conditions x
8.2.10.1. Overrun 8.2.10.2. Receive Overrun Behavior 8.2.10.3. Transmit Overrun Behavior 8.2.10.4. Underrun
8.3. Software Programming Model x
8.3.1. Overview 8.3.2. Supported Features 8.3.3. Unsupported Features 8.3.4. Configuration 8.3.5. 16550 UART API 8.3.6. Driver Examples
8.3.5. 16550 UART API x
8.3.5.1. Public APIs 8.3.5.2. Private APIs 8.3.5.3. UART Device Structure
8.4. Address Map and Register Descriptions x
8.4.1. rbr_thr_dll 8.4.2. ier_dlh 8.4.3. iir 8.4.4. fcr 8.4.5. lcr 8.4.6. mcr 8.4.7. lsr 8.4.8. msr 8.4.9. scr 8.4.10. afr 8.4.11. tx_low
9. UART Core x
9.1. Core Overview 9.2. Functional Description 9.3. Instantiating the Core 9.4. Software Programming Model 9.5. UART Core Revision History
9.2. Functional Description x
9.2.1. Avalon® -MM Agent Interface and Registers 9.2.2. RS-232 Interface 9.2.3. Transmitter Logic 9.2.4. Receiver Logic 9.2.5. Baud Rate Generation
9.3. Instantiating the Core x
9.3.1. Configuration Settings 9.3.2. Simulation Settings
9.3.1. Configuration Settings x
9.3.1.1. Baud Rate Options 9.3.1.2. Baud Rate (bps) Setting 9.3.1.3. Baud Rate Can Be Changed By Software Setting 9.3.1.4. Data Bits, Stop Bits, Parity 9.3.1.5. Synchronizer Stages 9.3.1.6. Streaming Data (DMA) Control
9.3.1.6. Streaming Data (DMA) Control x
9.3.1.6.1. Include End-of-Packet Register
9.3.2. Simulation Settings x
9.3.2.1. Simulated Transmitter Baud Rate 9.3.2.2. Simulation Considerations
9.4. Software Programming Model x
9.4.1. HAL System Library Support 9.4.2. Software Files 9.4.3. Register Map 9.4.4. Interrupt Behavior
9.4.1. HAL System Library Support x
9.4.1.1. Driver Options: Fast vs Small Implementations 9.4.1.2. ioctl() Operations 9.4.1.3. Limitations
9.4.1.1. Driver Options: Fast vs Small Implementations x
9.4.1.1.1. UART API 9.4.1.1.2. UART Device Structure
9.4.3. Register Map x
9.4.3.1. rxdata Register 9.4.3.2. txdata Register 9.4.3.3. status Register 9.4.3.4. control Register 9.4.3.5. divisor Register (Optional) 9.4.3.6. endofpacket Register (Optional)
10. Lightweight UART Core x
10.1. Core Overview 10.2. Functional Description 10.3. Configuration Parameters 10.4. Instantiating the Core 10.5. Software Programming Model 10.6. Lightweight UART Core Revision History
10.2. Functional Description x
10.2.1. Avalon® Memory-Mapped Agent Interface and Registers 10.2.2. RS-232 Interface 10.2.3. Transistor-Transistor Logic (TTL) Interface 10.2.4. Handshaking Signal (CTS/RTS Flow Control) 10.2.5. Transmitter Logic 10.2.6. Receiver Logic 10.2.7. Baud Rate Generation
10.3. Configuration Parameters x
10.3.1. Implement TXFIFO and RXFIFO in Register 10.3.2. Depth of TXFIFO and RXFIFO 10.3.3. Remaining RXFIFO Depth to Assert Almost Full 10.3.4. Include CTS/RTS
10.4. Instantiating the Core x
10.4.1. Baud Rate Options 10.4.2. Baud Rate (bps) Setting 10.4.3. Baud Rate Can Be Changed by Software Setting 10.4.4. Data Bits, Stop Bits, Parity 10.4.5. Synchronizer Stages 10.4.6. Streaming Data (DMA) Control
10.4.6. Streaming Data (DMA) Control x
10.4.6.1. Include End-of-Packet Register
10.5. Software Programming Model x
10.5.1. HAL System Library Support 10.5.2. Software Files 10.5.3. Supported Features 10.5.4. Register Map 10.5.5. Interrupt Behavior
10.5.1. HAL System Library Support x
10.5.1.1. Driver Options: Fast vs. Small Implementations 10.5.1.2. ioctl() Operations
10.5.1.1. Driver Options: Fast vs. Small Implementations x
10.5.1.1.1. UART API 10.5.1.1.2. UART Device Structure
10.5.4. Register Map x
10.5.4.1. Transmit Data FIFO (TXFIFO) 10.5.4.2. Receive data FIFO (RXFIFO) 10.5.4.3. Status Register 10.5.4.4. Control Register 10.5.4.5. Divisor Register 10.5.4.6. Endofpacket Register 10.5.4.7. RXFIFO Level Register (RXFIFO_LVL) 10.5.4.8. TXFIFO level register (TXFIFO_LVL)
11. JTAG UART Core x
11.1. Core Overview 11.2. Functional Description 11.3. Configuration 11.4. Software Programming Model 11.5. JTAG UART Core Revision History
11.2. Functional Description x
11.2.1. Avalon® Agent Interface and Registers 11.2.2. Read and Write FIFOs 11.2.3. JTAG Interface 11.2.4. Host-Target Connection 11.2.5. Operating System Code Page
11.3. Configuration x
11.3.1. Configuration Page
11.3.1. Configuration Page x
11.3.1.1. Write FIFO Settings 11.3.1.2. Read FIFO Settings
11.4. Software Programming Model x
11.4.1. HAL System Library Support 11.4.2. Software Files 11.4.3. Accessing the JTAG UART Core via a Host PC 11.4.4. Register Map 11.4.5. Interrupt Behavior
11.4.1. HAL System Library Support x
11.4.1.1. Driver Options: Fast vs. Small Implementations 11.4.1.2. ioctl() Operations
11.4.4. Register Map x
11.4.4.1. Data Register 11.4.4.2. Control Register
12. Intel FPGA Avalon® Mailbox Core x
12.1. Core Overview 12.2. Functional Description 12.3. Interface 12.4. HAL Driver 12.5. Intel FPGA Avalon® Mailbox Core Revision History
12.2. Functional Description x
12.2.1. Message Sending and Retrieval Process 12.2.2. Component Register Map
12.2.2. Component Register Map x
12.2.2.1. Command Register 12.2.2.2. Pointer Register 12.2.2.3. Status Register 12.2.2.4. Interrupt Masking Register
12.3. Interface x
12.3.1. Component Interface 12.3.2. Component Parameterization
12.4. HAL Driver x
12.4.1. Feature Description
12.4.1. Feature Description x
12.4.1.1. Component Configuration 12.4.1.2. Driver Implementation 12.4.1.3. Driver Examples
12.4.1.1. Component Configuration x
12.4.1.1.1. Interrupt Mode 12.4.1.1.2. Polling Mode
13. Intel FPGA Avalon® Mutex Core x
13.1. Core Overview 13.2. Functional Description 13.3. Configuration 13.4. Software Programming Model 13.5. Mutex API 13.6. Intel FPGA Avalon® Mutex Core Revision History
13.4. Software Programming Model x
13.4.1. Software Files 13.4.2. Hardware Access Routines
13.5. Mutex API x
13.5.1. altera_avalon_mutex_is_mine() 13.5.2. altera_avalon_mutex_first_lock() 13.5.3. altera_avalon_mutex_lock() 13.5.4. altera_avalon_mutex_open() 13.5.5. altera_avalon_mutex_trylock() 13.5.6. altera_avalon_mutex_unlock()
14. Intel FPGA Avalon® I2C (Host) Core x
14.1. Core Overview 14.2. Feature Description 14.3. Configuration Parameters 14.4. Interface 14.5. Registers 14.6. Reset and Clock Requirements 14.7. Functional Description 14.8. Intel FPGA Avalon® I2C (Host) Core API 14.9. Intel FPGA Avalon® I2C (Host) Core Revision History
14.2. Feature Description x
14.2.1. Supported Features 14.2.2. Unsupported Features
14.5. Registers x
14.5.1. Register Memory Map 14.5.2. Register Descriptions
14.5.2. Register Descriptions x
14.5.2.1. Transfer Command FIFO (TFR_CMD) 14.5.2.2. Receive Data FIFO (RX_DATA) 14.5.2.3. Control Register (CTRL) 14.5.2.4. Interrupt Status Enable Register (ISER) 14.5.2.5. Interrupt Status Register (ISR) 14.5.2.6. Status Register (STATUS) 14.5.2.7. TFR CMD FIFO Level (TFR CMD FIFO LVL) 14.5.2.8. RX Data FIFO Level (RX Data FIFO LVL) 14.5.2.9. SCL Low Count (SCL LOW) 14.5.2.10. SCL High Count (SCL HIGH) 14.5.2.11. SDA Hold Count (SDA HOLD)
14.7. Functional Description x
14.7.1. Overview 14.7.2. Configuring TFT_CMD Register Examples 14.7.3. I2C Serial Interface Connection 14.7.4. Avalon® -MM Agent Interface 14.7.5. Avalon® -ST Interface 14.7.6. Programming Model
14.7.2. Configuring TFT_CMD Register Examples x
14.7.2.1. 7-bit Addressing Mode 14.7.2.2. 10-bit Addressing Mode
14.7.2.1. 7-bit Addressing Mode x
14.7.2.1.1. Host Transmitter Writes 2 Bytes to Agent Receiver 14.7.2.1.2. Host Receiver Reads 2 Bytes from Agent Transmitter 14.7.2.1.3. Combine Format (Host Writes 1 Byte and Changes Direction to Read 2 Bytes)
14.7.2.2. 10-bit Addressing Mode x
14.7.2.2.1. Host Transmitter Writes 2 Bytes to Agent Receiver 14.7.2.2.2. Host Receiver Reads 2 Bytes from Agent Transmitter
14.8. Intel FPGA Avalon® I2C (Host) Core API x
14.8.1. Optional Status Retrieval API
15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core x
15.1. Core Overview 15.2. Functional Description 15.3. Platform Designer Parameters 15.4. Signals 15.5. How to Translate the Bridge's I2C Data and I2C I/O Ports to an I2C Interface 15.6. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core Revision History
15.2. Functional Description x
15.2.1. Block Diagram 15.2.2. N-byte Addressing 15.2.3. N-byte Addressing with N-bit Address Stealing 15.2.4. Read Operation 15.2.5. Write Operation 15.2.6. Interacting with Multi-Hosts
15.2.4. Read Operation x
15.2.4.1. Random Address Read 15.2.4.2. Sequential Address Read 15.2.4.3. Current Address Read
16. EPCS/EPCQA Serial Flash Controller Core x
16.1. Core Overview 16.2. Functional Description 16.3. Configuration 16.4. Interface Signals 16.5. Software Programming Model 16.6. Driver API 16.7. EPCS/EPCQA Serial Flash Controller Core Revision History
16.2. Functional Description x
16.2.1. Avalon® -MM Agent Interface and Registers
16.5. Software Programming Model x
16.5.1. HAL System Library Support 16.5.2. Software Files
17. Intel FPGA Serial Flash Controller Core x
17.1. Parameters 17.2. Registers 17.3. Nios® II and Nios® V Tools Support 17.4. Driver API 17.5. Intel FPGA Serial Flash Controller Core Revision History
17.1. Parameters x
17.1.1. Configuration Device Types 17.1.2. I/O Mode 17.1.3. Chip Selects 17.1.4. Interface Signals
17.2. Registers x
17.2.1. Register Memory Map 17.2.2. Register Descriptions
17.2.2. Register Descriptions x
17.2.2.1. FLASH_RD_STATUS 17.2.2.2. FLASH_RD_SID 17.2.2.3. FLASH_RD_RDID 17.2.2.4. FLASH_MEM_OP 17.2.2.5. FLASH_ISR 17.2.2.6. FLASH_IMR 17.2.2.7. FLASH_CHIP_SELECT
17.2.2.4. FLASH_MEM_OP x
17.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
17.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
17.2.2.4.1.1. Sector Protect 17.2.2.4.1.2. Sector Erase
17.3. Nios® II and Nios® V Tools Support x
17.3.1. Booting Nios® II from Flash 17.3.2. Nios® II and Nios® V HAL Drivers
17.3.1. Booting Nios® II from Flash x
17.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier 17.3.1.2. Boot Copier File 17.3.1.3. When Nios® II SBT will Append a Boot Copier 17.3.1.4. Creating HEX Programming File 17.3.1.5. Programming the Flash 17.3.1.6. Custom Boot Copiers 17.3.1.7. Executing in Place
18. Intel FPGA Serial Flash Controller II Core x
18.1. Parameters 18.2. Registers 18.3. Nios® II and Nios® V Tools Support 18.4. Driver API 18.5. Intel FPGA Serial Flash Controller II Core Revision History
18.1. Parameters x
18.1.1. Configuration Device Types 18.1.2. I/O Mode 18.1.3. Chip Selects 18.1.4. Interface Signals
18.2. Registers x
18.2.1. Register Memory Map 18.2.2. Register Descriptions
18.2.2. Register Descriptions x
18.2.2.1. FLASH_RD_STATUS 18.2.2.2. FLASH_RD_RDID 18.2.2.3. FLASH_MEM_OP 18.2.2.4. FLASH_CHIP_SELECT 18.2.2.5. EPCQ_FLAG_STATUS 18.2.2.6. DEVICE_ID_DATA_x
18.2.2.3. FLASH_MEM_OP x
18.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
18.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
18.2.2.3.1.1. Sector Protect 18.2.2.3.1.2. Sector Erase
18.3. Nios® II and Nios® V Tools Support x
18.3.1. Booting Nios® II from Flash 18.3.2. Nios® II and Nios® V HAL Drivers
18.3.1. Booting Nios® II from Flash x
18.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier 18.3.1.2. Boot Copier File 18.3.1.3. When Nios® II SBT will Append a Boot Copier 18.3.1.4. Creating HEX Programming File 18.3.1.5. Programming the Flash 18.3.1.6. Custom Boot Copiers 18.3.1.7. Executing in Place
19. Intel FPGA Generic QUAD SPI Controller Core x
19.1. Parameters 19.2. Registers 19.3. Nios® II and Nios® V Tools Support 19.4. Driver API 19.5. Intel FPGA Generic QUAD SPI Controller Core Revision History
19.1. Parameters x
19.1.1. Configuration Device Types 19.1.2. I/O Mode 19.1.3. Chip Selects 19.1.4. Interface Signals
19.2. Registers x
19.2.1. Register Memory Map 19.2.2. Register Descriptions
19.2.2. Register Descriptions x
19.2.2.1. FLASH_RD_STATUS 19.2.2.2. FLASH_RD_SID 19.2.2.3. FLASH_RD_RDID 19.2.2.4. FLASH_MEM_OP 19.2.2.5. FLASH_ISR 19.2.2.6. FLASH_IMR 19.2.2.7. FLASH_CHIP_SELECT
19.2.2.4. FLASH_MEM_OP x
19.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
19.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
19.2.2.4.1.1. Sector Protect 19.2.2.4.1.2. Sector Erase
19.3. Nios® II and Nios® V Tools Support x
19.3.1. Nios® II and Nios® V HAL Drivers
20. Intel FPGA Generic QUAD SPI Controller II Core x
20.1. Parameters 20.2. Interface Signals 20.3. Registers 20.4. Nios® II and Nios® V Tools Support 20.5. Driver API 20.6. Intel FPGA Generic QUAD SPI Controller II Core Revision History
20.1. Parameters x
20.1.1. Disable Dedicated Active Serial Interface 20.1.2. Enable SPI Pins Interface 20.1.3. Enable Flash Simulation Model 20.1.4. Configuration Device Types 20.1.5. I/O Mode 20.1.6. Chip Selects
20.3. Registers x
20.3.1. Register Memory Map 20.3.2. Register Descriptions
20.3.2. Register Descriptions x
20.3.2.1. FLASH_RD_STATUS 20.3.2.2. FLASH_RD_RDID 20.3.2.3. FLASH_MEM_OP 20.3.2.4. FLASH_CHIP_SELECT 20.3.2.5. EPCQ_FLAG_STATUS 20.3.2.6. DEVICE_ID_DATA_x
20.3.2.3. FLASH_MEM_OP x
20.3.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
20.3.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
20.3.2.3.1.1. Sector Protect 20.3.2.3.1.2. Sector Erase
20.4. Nios® II and Nios® V Tools Support x
20.4.1. Nios® II and Nios® V HAL Drivers
21. Interval Timer Core x
21.1. Core Overview 21.2. Functional Description 21.3. IP Parameters 21.4. Driver Implementation 21.5. Register Map 21.6. HAL APIs and Macros 21.7. Interval Timer Core Revision History
21.2. Functional Description x
21.2.1. Avalon® -MM Agent Interface
21.3. IP Parameters x
21.3.1. Timeout Period 21.3.2. Counter Size 21.3.3. Configuring the Timer as a Watchdog Timer
21.4. Driver Implementation x
21.4.1. Interrupt Behavior
22. Intel FPGA Avalon FIFO Memory Core x
22.1. Core Overview 22.2. Functional Description 22.3. Configuration 22.4. Software Programming Model 22.5. Programming with the Intel FPGA Avalon FIFO Memory 22.6. Intel FPGA Avalon FIFO Memory API 22.7. Intel FPGA Avalon FIFO Memory Core Revision History
22.2. Functional Description x
22.2.1. Avalon® -MM Write Agent to Avalon® -MM Read Agent 22.2.2. Avalon® -ST Sink to Avalon® -ST Source 22.2.3. Avalon® -MM Write Agent to Avalon® -ST Source 22.2.4. Avalon® -ST Sink to Avalon® -MM Read Agent 22.2.5. Status Interface 22.2.6. Clocking Modes
22.3. Configuration x
22.3.1. FIFO Settings 22.3.2. Interface Parameters 22.3.3. Interface Signals
22.4. Software Programming Model x
22.4.1. HAL System Library Support 22.4.2. Software Files
22.5. Programming with the Intel FPGA Avalon FIFO Memory x
22.5.1. Software Control 22.5.2. Software Example
22.6. Intel FPGA Avalon FIFO Memory API x
22.6.1. altera_avalon_fifo_init() 22.6.2. altera_avalon_fifo_read_status() 22.6.3. altera_avalon_fifo_read_ienable() 22.6.4. altera_avalon_fifo_read_almostfull() 22.6.5. altera_avalon_fifo_read_almostempty() 22.6.6. altera_avalon_fifo_read_event() 22.6.7. altera_avalon_fifo_read_level() 22.6.8. altera_avalon_fifo_clear_event() 22.6.9. altera_avalon_fifo_write_ienable() 22.6.10. altera_avalon_fifo_write_almostfull() 22.6.11. altera_avalon_fifo_write_almostempty() 22.6.12. altera_avalon_write_fifo() 22.6.13. altera_avalon_write_other_info() 22.6.14. altera_avalon_fifo_read_fifo() 22.6.15. altera_avalon_fifo_read_other_info()
23. On-Chip Memory (RAM and ROM) Intel FPGA IP x
23.1. Core Overview 23.2. Component-Level Design for On-Chip Memory 23.3. Platform Designer System-Level Design for On-Chip Memory 23.4. Simulation for On-Chip Memory 23.5. Quartus® Prime Project-Level Design for On-Chip Memory 23.6. Board-Level Design for On-Chip Memory 23.7. Example Design with On-Chip Memory 23.8. On-Chip Memory (RAM and ROM) Intel FPGA IP Revision History
23.2. Component-Level Design for On-Chip Memory x
23.2.1. Memory Type 23.2.2. Size 23.2.3. Read Latency 23.2.4. ROM/RAM Memory Protection 23.2.5. ECC Parameter 23.2.6. Memory Initialization
24. On-Chip Memory II (RAM or ROM) Intel FPGA IP x
24.1. Core Overview 24.2. Embedded Memory Architecture and Features 24.3. Component-Level Configurations 24.4. Interface Signals 24.5. Control and Status Registers 24.6. Software Programming Model 24.7. Platform Designer System-Level Design for On-Chip Memory II 24.8. Simulation for On-Chip Memory II 24.9. Quartus® Prime Project-Level Design for On-Chip Memory II 24.10. Board-Level Design for On-Chip Memory II 24.11. Example Design with On-Chip Memory II 24.12. On-Chip Memory II (RAM and ROM) Intel FPGA IP Revision History
24.3. Component-Level Configurations x
24.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration 24.3.2. AXI-4 On-Chip Memory II Configuration
24.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration x
24.3.1.1. Avalon Memory-Mapped Interface 24.3.1.2. Memory Type 24.3.1.3. Clock Enable 24.3.1.4. Size 24.3.1.5. Read During Write Mode 24.3.1.6. Read Latency 24.3.1.7. ROM/RAM Memory Protection 24.3.1.8. ECC 24.3.1.9. Memory Initialization
24.3.2. AXI-4 On-Chip Memory II Configuration x
24.3.2.1. AXI-4 Interface 24.3.2.2. Memory Type 24.3.2.3. Clock Enable 24.3.2.4. Size 24.3.2.5. Read During Write Mode 24.3.2.6. ROM/RAM Memory Protection 24.3.2.7. Memory Initialization 24.3.2.8. ECC
24.3.2.8. ECC x
24.3.2.8.1. Supported ECC Configuration 24.3.2.8.2. Supported ECC Features 24.3.2.8.3. ECC Status Reporting 24.3.2.8.4. ECC Encoder Bypass 24.3.2.8.5. Read Modify Write
24.4. Interface Signals x
24.4.1. Avalon Memory-Mapped Interface Signals 24.4.2. Avalon Memory-Mapped Interface Timing Diagram 24.4.3. AXI-4 Lite Interface Signals 24.4.4. AXI-4 Interface Signals 24.4.5. AXI Interface Timing Diagram
24.5. Control and Status Registers x
24.5.1. Register Memory Map 24.5.2. Register Descriptions
24.6. Software Programming Model x
24.6.1. Read ECC Error Status FIFO 24.6.2. Enable Encoder Bypass Feature
25. PIO Core x
25.1. Core Overview 25.2. Functional Description 25.3. Example Configurations 25.4. Configuration 25.5. Software Programming Model 25.6. PIO Core Revision History
25.2. Functional Description x
25.2.1. Data Input and Output 25.2.2. Edge Capture 25.2.3. IRQ Generation
25.3. Example Configurations x
25.3.1. Avalon® -MM Interface
25.4. Configuration x
25.4.1. Basic Settings 25.4.2. Input Options 25.4.3. Simulation
25.4.1. Basic Settings x
25.4.1.1. Width 25.4.1.2. Direction 25.4.1.3. Output Port Reset Value 25.4.1.4. Output Register
25.4.2. Input Options x
25.4.2.1. Edge Capture Register 25.4.2.2. Interrupt
25.5. Software Programming Model x
25.5.1. Software Files 25.5.2. Register Map 25.5.3. Interrupt Behavior 25.5.4. Software Files
25.5.2. Register Map x
25.5.2.1. data Register 25.5.2.2. direction Register 25.5.2.3. interruptmask Register 25.5.2.4. edgecapture Register 25.5.2.5. outset and outclear Register
26. PLL Cores x
26.1. Core Overview 26.2. Functional Description 26.3. Instantiating the Avalon® ALTPLL Core 26.4. Instantiating the PLL Core 26.5. Hardware Simulation Considerations 26.6. Register Definitions and Bit List 26.7. PLL Cores Revision History
26.2. Functional Description x
26.2.1. ALTPLL IP Core 26.2.2. Clock Outputs 26.2.3. PLL Status and Control Signals 26.2.4. System Reset Considerations
26.6. Register Definitions and Bit List x
26.6.1. Status Register 26.6.2. Control Register 26.6.3. Phase Reconfig Control Register
27. DMA Controller Core x
27.1. Core Overview 27.2. Functional Description 27.3. Parameters 27.4. Software Programming Model 27.5. DMA Controller Core Revision History
27.2. Functional Description x
27.2.1. Setting Up DMA Transactions 27.2.2. The Host Read and Write Ports 27.2.3. Addressing and Address Incrementing
27.3. Parameters x
27.3.1. DMA Parameters (Basic) 27.3.2. Advanced Options
27.4. Software Programming Model x
27.4.1. HAL System Library Support 27.4.2. Software Files 27.4.3. Register Map 27.4.4. Interrupt Behavior
28. Modular Scatter-Gather DMA Core x
28.1. Core Overview 28.2. Feature Description 28.3. mSGDMA Descriptors 28.4. mSGDMA Descriptors with Prefetcher 28.5. mSGDMA IP Interface 28.6. mSGDMA Interrupt 28.7. Register Map of mSGDMA 28.8. Parameters 28.9. mSGDMA Programming Model 28.10. mSGDMA Prefetcher Programming Model 28.11. Driver Implementation 28.12. Example Code Using mSGDMA Core 28.13. Modular Scatter-Gather DMA Prefetcher Core 28.14. Modular Scatter-Gather DMA Dispatcher Core 28.15. Modular Scatter-Gather DMA Write Master Core 28.16. Modular Scatter-Gather DMA Read Master Core 28.17. Modular Scatter-Gather DMA Core Revision History
28.2. Feature Description x
28.2.1. mSGDMA IP with Prefetcher Disabled 28.2.2. mSGDMA IP with Prefetcher Enabled
28.3. mSGDMA Descriptors x
28.3.1. Read and Write Address Fields 28.3.2. Length Field 28.3.3. Sequence Number Field 28.3.4. Read and Write Burst Count Fields 28.3.5. Read and Write Stride Fields 28.3.6. Control Field
28.4. mSGDMA Descriptors with Prefetcher x
28.4.1. Descriptor Format 28.4.2. Responder Descriptor Format 28.4.3. Descriptor Fields Definition 28.4.4. Descriptor Processing with Prefetcher Enabled
28.5. mSGDMA IP Interface x
28.5.1. Control and Status Register Agent Interface 28.5.2. Source and Destination Data Path Interface 28.5.3. Prefetcher Disabled Mode Interface 28.5.4. Prefetcher Enabled Mode Interface 28.5.5. IP Interface Signals
28.7. Register Map of mSGDMA x
28.7.1. Status Register (Offset 0x0) 28.7.2. Control Register (Offset 0x4) 28.7.3. Read and Write Fill Level Register (Offset 0x8) 28.7.4. Response Fill Level Register (Offset 0xC) 28.7.5. Sequence Number Register (Offset 0x10) 28.7.6. Component Configuration 1 Register (Offset 0x14) 28.7.7. Component Configuration 2 Register (Offset 0x18) 28.7.8. Component Specification Register (Offset 0x1C) 28.7.9. Response Register (when MM response port is enabled) 28.7.10. Prefetcher Register
28.8. Parameters x
28.8.1. mSGDMA Parameter Editor
28.9. mSGDMA Programming Model x
28.9.1. Stop DMA Operation 28.9.2. Stop Descriptor Operation 28.9.3. Recovery from Stopped on Error and Stopped on Early Termination
28.10. mSGDMA Prefetcher Programming Model x
28.10.1. Setting up Descriptor and mSGDMA Configuration Flow 28.10.2. Resetting Prefetcher Core Flow
28.11. Driver Implementation x
28.11.1. alt_msgdma_standard_descriptor_async_transfer 28.11.2. alt_msgdma_extended_descriptor_async_transfer 28.11.3. alt_msgdma_standard_descriptor_sync_transfer 28.11.4. alt_msgdma_extended_descriptor_sync_transfer 28.11.5. alt_msgdma_descriptor_sync_transfer 28.11.6. alt_msgdma_construct_standard_st_to_mm_descriptor 28.11.7. alt_msgdma_construct_standard_mm_to_st_descriptor 28.11.8. alt_msgdma_construct_standard_mm_to_mm_descriptor 28.11.9. alt_msgdma_construct_extended_st_to_mm_descriptor 28.11.10. alt_msgdma_construct_extended_mm_to_st_descriptor 28.11.11. alt_msgdma_construct_extended_mm_to_mm_descriptor 28.11.12. alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor 28.11.13. alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor 28.11.14. alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor 28.11.15. alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor 28.11.16. alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor 28.11.17. alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor 28.11.18. alt_msgdma_prefetcher_add_standard_desc_to_list 28.11.19. alt_msgdma_prefetcher_add_extended_desc_to_list 28.11.20. alt_msgdma_start_prefetcher_with_std_desc_list 28.11.21. alt_msgdma_start_prefetcher_with_extd_desc_list 28.11.22. alt_msgdma_register_callback 28.11.23. alt_msgdma_open 28.11.24. alt_msgdma_init
28.13. Modular Scatter-Gather DMA Prefetcher Core x
28.13.1. Functional Description 28.13.2. Descriptor Format 28.13.3. Registers 28.13.4. Interfaces 28.13.5. Software Programming Model 28.13.6. Parameters
28.13.1. Functional Description x
28.13.1.1. Supported Features 28.13.1.2. Architecture Overview
28.13.2. Descriptor Format x
28.13.2.1. Descriptor Fields Definition 28.13.2.2. Descriptor Processing
28.13.3. Registers x
28.13.3.1. Register Map 28.13.3.2. Control Register 28.13.3.3. Descriptor Polling Frequency 28.13.3.4. Status
28.13.4. Interfaces x
28.13.4.1. Avalon® -MM Read Descriptor 28.13.4.2. Avalon® -MM Write Descriptor 28.13.4.3. Avalon® -MM CSR 28.13.4.4. Avalon® -ST Descriptor Source 28.13.4.5. Avalon® -ST Response 28.13.4.6. IRQ Interface
28.13.5. Software Programming Model x
28.13.5.1. Setting up Descriptor and mSGDMA Configuration Flow 28.13.5.2. Resetting Prefetcher Core Flow
28.14. Modular Scatter-Gather DMA Dispatcher Core x
28.14.1. Block Diagram 28.14.2. Functional Description 28.14.3. mSGDMA Descriptors 28.14.4. Interfaces 28.14.5. Interrupts 28.14.6. mSGDMA Programming Model 28.14.7. Register Descriptions
28.14.3. mSGDMA Descriptors x
28.14.3.1. Descriptor Format 28.14.3.2. Descriptor Fields Definition
28.14.4. Interfaces x
28.14.4.1. IP Interface 28.14.4.2. Resets 28.14.4.3. Clocks
28.14.4.1. IP Interface x
28.14.4.1.1. Control and Status Register Agent Interface (CSR) 28.14.4.1.2. Descriptor Interface 28.14.4.1.3. Response Interface
28.14.6. mSGDMA Programming Model x
28.14.6.1. Stop DMA Operation 28.14.6.2. Stop Descriptor Operation 28.14.6.3. Recovery from Stopped on Error and Stopped on Early Termination
28.14.7. Register Descriptions x
28.14.7.1. Register Map of mSGDMA Dispatcher IP
28.14.7.1. Register Map of mSGDMA Dispatcher IP x
28.14.7.1.1. Status Register (Offset 0x0) 28.14.7.1.2. Control Register (Offset 0x4) 28.14.7.1.3. Read and Write Fill Level Register (Offset 0x8) 28.14.7.1.4. Response Fill Level Register (Offset 0xC) 28.14.7.1.5. Sequence Number Register (Offset 0x10) 28.14.7.1.6. Component Configuration 1 Register (Offset 0x14) 28.14.7.1.7. Component Configuration 2 Register (Offset 0x18) 28.14.7.1.8. Component Specification Register (Offset 0x1C) 28.14.7.1.9. Response Register (when MM response port is enabled)
28.15. Modular Scatter-Gather DMA Write Master Core x
28.15.1. Block Diagram 28.15.2. Functional Description 28.15.3. Interfaces 28.15.4. Parameters
28.15.2. Functional Description x
28.15.2.1. Command Fields Definition 28.15.2.2. Response Fields Definition
28.15.3. Interfaces x
28.15.3.1. Data Write Master Interface (data_write_master) 28.15.3.2. Data Sink Interface (data_sink) 28.15.3.3. Write Command Sink Interface (command_sink) 28.15.3.4. Write Response Source Interface (response_source)
28.16. Modular Scatter-Gather DMA Read Master Core x
28.16.1. Block Diagram 28.16.2. Functional Description 28.16.3. Interfaces 28.16.4. Parameters
28.16.2. Functional Description x
28.16.2.1. Command Fields Definition 28.16.2.2. Response Fields Definition
28.16.3. Interfaces x
28.16.3.1. Data Read Master Interface (data_read_master) 28.16.3.2. Data Source Interface (data_source) 28.16.3.3. Read Command Sink Interface (command_sink) 28.16.3.4. Read Response Source Interface (response_source)
29. Scatter-Gather DMA Controller Core x
29.1. Core Overview 29.2. Resource Usage and Performance 29.3. Functional Description 29.4. Parameters 29.5. Simulation Considerations 29.6. Software Programming Model 29.7. Programming with SG-DMA Controller 29.8. Scatter-Gather DMA Controller Core Revision History
29.1. Core Overview x
29.1.1. Example Systems 29.1.2. Comparison of SG-DMA Controller Core and DMA Controller Core
29.3. Functional Description x
29.3.1. Functional Blocks and Configurations 29.3.2. DMA Descriptors 29.3.3. Error Conditions
29.6. Software Programming Model x
29.6.1. HAL System Library Support 29.6.2. Software Files 29.6.3. Register Maps 29.6.4. DMA Descriptors 29.6.5. Timeouts
29.7. Programming with SG-DMA Controller x
29.7.1. Data Structure 29.7.2. SG-DMA API 29.7.3. alt_avalon_sgdma_do_async_transfer() 29.7.4. alt_avalon_sgdma_do_sync_transfer() 29.7.5. alt_avalon_sgdma_construct_mem_to_mem_desc() 29.7.6. alt_avalon_sgdma_construct_stream_to_mem_desc() 29.7.7. alt_avalon_sgdma_construct_mem_to_stream_desc() 29.7.8. alt_avalon_sgdma_enable_desc_poll() 29.7.9. alt_avalon_sgdma_disable_desc_poll() 29.7.10. alt_avalon_sgdma_check_descriptor_status() 29.7.11. alt_avalon_sgdma_register_callback() 29.7.12. alt_avalon_sgdma_start() 29.7.13. alt_avalon_sgdma_stop() 29.7.14. alt_avalon_sgdma_open()
30. Video Sync Generator and Pixel Converter Cores x
30.1. Core Overview 30.2. Video Sync Generator 30.3. Pixel Converter 30.4. Hardware Simulation Considerations 30.5. Video Sync Generator and Pixel Converter Cores Revision History
30.2. Video Sync Generator x
30.2.1. Functional Description 30.2.2. Parameters 30.2.3. Signals 30.2.4. Timing Diagrams
30.3. Pixel Converter x
30.3.1. Functional Description 30.3.2. Parameters 30.3.3. Signals
31. Intel FPGA Interrupt Latency Counter Core x
31.1. Core Overview 31.2. Feature Description 31.3. Component Interface 31.4. Component Parameterization 31.5. Software Access 31.6. Implementation Details 31.7. IP Caveats 31.8. Intel FPGA Interrupt Latency Counter Core Revision History
31.2. Feature Description x
31.2.1. Avalon® -MM Compliant CSR Registers 31.2.2. 32-bit Counter 31.2.3. Interrupt Detector
31.2.1. Avalon® -MM Compliant CSR Registers x
31.2.1.1. Control Register 31.2.1.2. Frequency Register 31.2.1.3. Counter Stop Registers 31.2.1.4. Latency Data Registers 31.2.1.5. Data Valid Registers 31.2.1.6. IRQ Active Registers
31.5. Software Access x
31.5.1. Routine for Level Sensitive Interrupts 31.5.2. Routine for Edge/Pulse Sensitive Interrupts
31.6. Implementation Details x
31.6.1. Interrupt Latency Counter Architecture
32. Performance Counter Unit Core x
32.1. Core Overview 32.2. Functional Description 32.3. Configuration 32.4. Hardware Simulation Considerations 32.5. Software Programming Model 32.6. Performance Counter API 32.7. Performance Counter Core Revision History
32.2. Functional Description x
32.2.1. Section Counters 32.2.2. Global Counter 32.2.3. Register Map 32.2.4. System Reset
32.3. Configuration x
32.3.1. Define Counters 32.3.2. Multiple Clock Domain Considerations
32.5. Software Programming Model x
32.5.1. Software Files 32.5.2. Using the Performance Counter 32.5.3. Interrupt Behavior
32.6. Performance Counter API x
32.6.1. PERF_RESET() 32.6.2. PERF_START_MEASURING() 32.6.3. PERF_STOP_MEASURING() 32.6.4. PERF_BEGIN() 32.6.5. PERF_END() 32.6.6. perf_print_formatted_report() 32.6.7. perf_get_total_time() 32.6.8. perf_get_section_time() 32.6.9. perf_get_num_starts() 32.6.10. alt_get_cpu_freq()
33. Vectored Interrupt Controller Core x
33.1. Core Overview 33.2. Functional Description 33.3. Register Maps 33.4. Parameters 33.5. Intel FPGA HAL Software Programming Model 33.6. Implementing the VIC in Platform Designer 33.7. Example Designs 33.8. Advanced Topics 33.9. Vectored Interrupt Controller Core Revision History
33.2. Functional Description x
33.2.1. External Interfaces 33.2.2. Functional Blocks 33.2.3. Daisy Chaining VIC Cores 33.2.4. Latency Information
33.2.1. External Interfaces x
33.2.1.1. clk 33.2.1.2. irq_input 33.2.1.3. interrupt_controller_out 33.2.1.4. interrupt_controller_in 33.2.1.5. csr_access
33.2.2. Functional Blocks x
33.2.2.1. Interrupt Request Block 33.2.2.2. Priority Processing Block 33.2.2.3. Vector Generation Block
33.5. Intel FPGA HAL Software Programming Model x
33.5.1. Software Files 33.5.2. Macros 33.5.3. Data Structure 33.5.4. VIC API 33.5.5. Run-time Initialization 33.5.6. Board Support Package
33.5.4. VIC API x
33.5.4.1. alt_vic_sw_interrupt_set() 33.5.4.2. alt_vic_sw_interrupt_clear() 33.5.4.3. alt_vic_sw_interrupt_status() 33.5.4.4. alt_vic_irq_set_level()
33.5.6. Board Support Package x
33.5.6.1. altera_vic_driver.enable_preemption 33.5.6.2. altera_vic_driver.enable_preemption_into_new_register_set 33.5.6.3. altera_vic_driver.enable_preemption_rs_<n> 33.5.6.4. altera_vic_driver.linker_section 33.5.6.5. altera_vic_driver.<name>.vec_size 33.5.6.6. altera_vic_driver.<name>.irq<n>_rrs 33.5.6.7. altera_vic_driver.<name>.irq<n>_ril 33.5.6.8. altera_vic_driver.<name>.irq<n>_rnmi 33.5.6.9. Default Settings for RRS and RIL 33.5.6.10. VIC BSP Design Rules for Intel FPGA HAL Implementation 33.5.6.11. RTOS Considerations
33.6. Implementing the VIC in Platform Designer x
33.6.1. Adding VIC Hardware 33.6.2. Software for VIC
33.6.1. Adding VIC Hardware x
33.6.1.1. Adding the EIC Interface Shadow Register Set 33.6.1.2. VIC Instantiation, Parameterization, and Connection
33.6.1.2. VIC Instantiation, Parameterization, and Connection x
33.6.1.2.1. Instantiation 33.6.1.2.2. Parameterization 33.6.1.2.3. VIC Connections
33.6.2. Software for VIC x
33.6.2.1. alt_ic_isr_register() versus alt_irq_register()
33.7. Example Designs x
33.7.1. Example Description 33.7.2. Example Usage 33.7.3. Software Description 33.7.4. Positioning the ISR in Vector Table 33.7.5. Latency Measurement with the Performance Counter
33.7.4. Positioning the ISR in Vector Table x
33.7.4.1. Increase the Vector Table Entry Size 33.7.4.2. Do Not Register the ISR 33.7.4.3. Insert ISR in Vector Table
33.8. Advanced Topics x
33.8.1. Real Time Latency Concerns 33.8.2. Software Interrupt
33.8.1. Real Time Latency Concerns x
33.8.1.1. Pipeline Latency 33.8.1.2. Cause Latency 33.8.1.3. Selection Latency 33.8.1.4. Funnel Latency 33.8.1.5. Compiler-Related Latency
34. System ID Peripheral Core x
34.1. Core Overview 34.2. Functional Description 34.3. Configuration 34.4. Software Programming Model 34.5. System ID Core Revision History
34.3. Configuration x
34.3.1. System ID 34.3.2. System Generation Timestamp
34.4. Software Programming Model x
34.4.1. alt_avalon_sysid_qsys_test()
35. Intel FPGA GMII to RGMII Converter Core x
35.1. Core Overview 35.2. Feature Description 35.3. Parameters 35.4. Intel FPGA GMII to RGMII Converter Core Interface 35.5. Functional Description 35.6. Intel FPGA HPS EMAC Interface Splitter Core 35.7. Intel FPGA GMII to RGMII Converter Core Revision History
35.2. Feature Description x
35.2.1. Supported Features 35.2.2. Unsupported Features
35.3. Parameters x
35.3.1. IP Configuration Parameter
35.5. Functional Description x
35.5.1. Architecture
35.5.1. Architecture x
35.5.1.1. Data Path 35.5.1.2. Clock Scheme
35.5.1.2. Clock Scheme x
35.5.1.2.1. Transmit 35.5.1.2.2. Receive
35.6. Intel FPGA HPS EMAC Interface Splitter Core x
35.6.1. Parameter
35.6.1. Parameter x
35.6.1.1. System Info Parameter 35.6.1.2. HDL Parameter 35.6.1.3. Interface Signals 35.6.1.4. Register 35.6.1.5. Avalon® -MM Agent Interface
35.6.1.4. Register x
35.6.1.4.1. Register Memory Map 35.6.1.4.2. Register Description
36. HPS GMII to RGMII Adapter IP x
36.1. Core Overview 36.2. Feature Description 36.3. Parameters 36.4. HPS GMII to RGMII Adapter IP Interface 36.5. Functional Description 36.6. HPS GMII to RGMII Adapter IP Revision History
36.2. Feature Description x
36.2.1. Supported Features 36.2.2. Unsupported Features
36.3. Parameters x
36.3.1. IP Configuration Parameter
36.5. Functional Description x
36.5.1. Architecture
36.5.1. Architecture x
36.5.1.1. Data Path 36.5.1.2. Clock Scheme
36.5.1.2. Clock Scheme x
36.5.1.2.1. Transmit 36.5.1.2.2. Receive
37. Intel FPGA MII to RMII Converter Core x
37.1. Supported Features 37.2. Interface Signals 37.3. Parameters 37.4. Functional Description 37.5. Intel FPGA MII to RMII Converter Core Revision History
37.4. Functional Description x
37.4.1. Clocking Scheme 37.4.2. Transmit Interface 37.4.3. Receive Interface
38. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core IP x
38.1. Core Overview 38.2. Feature Description 38.3. Core Architecture 38.4. Configuration Parameters 38.5. Interface 38.6. Registers 38.7. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge IP Core Revision History
38.2. Feature Description x
38.2.1. Supported Features
38.3. Core Architecture x
38.3.1. Data Path 38.3.2. Clock Scheme 38.3.3. MAC Speed 38.3.4. Transmit Elastic Buffer 38.3.5. Avalon® Memory-Mapped Interface Agent Interface 38.3.6. Programming Model
38.3.4. Transmit Elastic Buffer x
38.3.4.1. GMII to MII Mode Transition
38.6. Registers x
38.6.1. Register Memory Map 38.6.2. Register Description
39. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core x
39.1. Supported Features 39.2. Functional Description 39.3. Interface Signals 39.4. Register Memory Map and Description 39.5. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core Revision History
40. Intel FPGA MSI to GIC Generator Core x
40.1. Core Overview 40.2. Background 40.3. Feature Description 40.4. Intel FPGA MSI to GIC Generator Core Revision History
40.3. Feature Description x
40.3.1. Interrupt Servicing Process 40.3.2. Registers of Component 40.3.3. Unsupported Feature
40.3.2. Registers of Component x
40.3.2.1. Status Register 40.3.2.2. Error Register 40.3.2.3. Interrupt Mask Register
41. Cache Coherency Translator IP x
41.1. Core Overview 41.2. IP Parameters 41.3. Use Case 41.4. Functional Description 41.5. Interface Signals 41.6. Clocking 41.7. Reset 41.8. Clock and Reset Signals 41.9. Register Description 41.10. Cache Coherency Translator IP Revision History
41.4. Functional Description x
41.4.1. Fixed Value 41.4.2. GPIO Mode 41.4.3. CSR Mode
42. Altera ACE5-Lite Cache Coherency Translator x
42.1. Core Overview 42.2. IP Parameters 42.3. Use Case 42.4. Functional Description 42.5. Interface Signals 42.6. Clocking 42.7. Reset 42.8. Clock and Reset Signals 42.9. Register Description 42.10. Altera ACE5-Lite Cache Coherency Translator Revision History
1. Introduction
2. Avalon® -ST Serial Peripheral Interface Core
3. SPI Core
4. SPI Agent/JTAG to Avalon® Host Bridge Cores
5. Intel eSPI Agent Core
6. eSPI to LPC Bridge Core
7. Ethernet MDIO Core
8. Intel FPGA 16550 Compatible UART Core
9. UART Core
10. Lightweight UART Core
11. JTAG UART Core
12. Intel FPGA Avalon® Mailbox Core
13. Intel FPGA Avalon® Mutex Core
14. Intel FPGA Avalon® I2C (Host) Core
15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core
16. EPCS/EPCQA Serial Flash Controller Core
17. Intel FPGA Serial Flash Controller Core
18. Intel FPGA Serial Flash Controller II Core
19. Intel FPGA Generic QUAD SPI Controller Core
20. Intel FPGA Generic QUAD SPI Controller II Core
21. Interval Timer Core
22. Intel FPGA Avalon FIFO Memory Core
23. On-Chip Memory (RAM and ROM) Intel FPGA IP
24. On-Chip Memory II (RAM or ROM) Intel FPGA IP
25. PIO Core
26. PLL Cores
27. DMA Controller Core
28. Modular Scatter-Gather DMA Core
29. Scatter-Gather DMA Controller Core
30. Video Sync Generator and Pixel Converter Cores
31. Intel FPGA Interrupt Latency Counter Core
32. Performance Counter Unit Core
33. Vectored Interrupt Controller Core
34. System ID Peripheral Core
35. Intel FPGA GMII to RGMII Converter Core
36. HPS GMII to RGMII Adapter IP
37. Intel FPGA MII to RMII Converter Core
38. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core IP
39. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core
40. Intel FPGA MSI to GIC Generator Core
41. Cache Coherency Translator IP
42. Altera ACE5-Lite Cache Coherency Translator

28.15.4. Parameters

The modular SGDMA has numerous configuration options to enable various functional units. Unnecessary functionality can be disabled to save resources and increase the frequency of the write master IP. This section will discuss the various options for the write master IP.

Note: There are options that require modular SGDMA dispatcher module to have the extended features support enabled.
Table 451.  mSGDMA Write Master IP Parameters
Parameter Display Name Parameter Name Allowable Range Default Value Description
Transfer Options
Data Width DATA_WIDTH 8, 16, 32, 64, 128, 256, 512, 1024 32 Width of the streaming and memory mapped data path.
No Byteenables GUI_NO_BYTEENABLES Enable, Disable Disable

Enable to force byte enables to always high.

Note: Applicable only for Aligned Accesses and Data Width larger than 8.
Note: This parameter is only available in Quartus Prime Pro Edition software.
Length Width LENGTH_WIDTH 3—32 32

Width of the length register.

Note: Reduce the length width to increase Fmax and the logic footprint.
FIFO Depth FIFO_DEPTH 16, 32, 64, 128, 256, 512, 1024, 2048, 4096 32

Depth of internal data FIFO.

The FIFO depth setting must be at least four times the maximum burst count setting.
Use pre-determined host address width USE_FIX_ADDRESS_WIDTH Enable, Disable Disable

When enabled, host address width is configurable based on parameter Pre-determined host address width.

When disabled, host address width is set to 32-bit.
Pre-determined host address width FIX_ADDRESS_WIDTH 1—64 32

Minimum host address width that is required to address memory agent.

Note: Applicable only when parameter Use pre-determined host address width is enabled.
Stride Addressing Enable 74 STRIDE_ENABLE Enable, Disable Disable

Enable stride addressing to control the address incrementing. Stride addressing allows access to data that is interleaved in memory.

Stride addressing cannot be enabled with burst capabilities or unaligned accesses enabled.
Stride Width74 GUI_STRIDE_WIDTH 1 – 16 1

Set the stride width for the maximum address increment.

The stride width must be set to at least floor(log2(maximum stride)) + 1.

Note: Applicable only when parameter Stride Addressing Enable is enabled.
Burst Enable BURST_ENABLE Enable, Disable Disable

Enable burst transfer to turn on the bursting capabilities of the write host.

Bursting must not be enabled when stride is also enabled.
Maximum Burst Count GUI_MAX_BURST_COUNT 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 2

Maximum burst count.

The maximum burst count must be less than or equal to a quarter of the FIFO depth setting.

Note: Applicable only when parameter Burst Enable is enabled.
Programmable Burst Enable74 GUI_PROGRAMMABLE_BURST_ENABLE Enable, Disable Disable

Enable re-programming of the burst count to 1, 2, 4, 8, 16, 32, 64, or 128 for each descriptor. The burst count that is programmed must be less than or equal to the maximum burst count setting.

Note: You cannot use this setting and force burst alignment support concurrently.
Note: Applicable only when parameter Burst Enable is enabled.
Force Burst Alignment Enable GUI_BURST_WRAPPING_SUPPORT Enable, Disable Disable

Enable force burst alignment to force the write host to post bursts of length 1 until the address is aligned to the next burst boundary. When connecting the write master IP to a burst wrapping slave ports (SDRAM), you must enable this setting.

Note: If this feature is enabled, it’ll caused performance degradation if the address is not burst aligned.
Note: You cannot use this setting and programmable burst capabilities concurrently.
Note: Applicable only when parameter Burst Enable is enabled.
Enable Write Response WRITE_RESPONSE_ENABLE Enable, Disable Disable

When enabled, it will turn on the write response features of the write master. Notification on mSDMA transfer completion is issued to the host only when all the outstanding writes have been responded.

Note: This parameter is only available in Quartus Prime Pro Edition software.
Memory Access Options
Transfer Type TRANSFER_TYPE

Full Word Accesses Only,

Aligned Accesses,

Unaligned Accesses

 Aligned Accesses

Supported transaction type.

  • Full Word Accesses Only: When full word accesses only is enabled, you must provide a write address that is aligned. You must also provide a transfer length is that is a multiple of the data width. This memory access mode results in the smallest hardware footprint and highest frequency.
  • Aligned Accesses: When aligned accesses is enabled, you must provide a write address that is aligned. You can provide any transfer length.
  • Unaligned Accesses: When unaligned accesses is enabled, you can provide any write address or transfer length. This memory access mode results in the largest hardware footprint and lowest frequency.
Streaming Options
Packet Support Enable PACKET_ENABLE Enable, Disable Disable Enable packetized streaming output, which includes the start of packet (SOP), end of packet (EOP) and empty signals.
Error Enable ERROR_ENABLE Enable, Disable Disable Enable error support to include a streaming error input.
Error Width ERROR_WIDTH 1, 2, 3, 4, 5, 6, 7, 8 8

Error field width. Set the error width according to the number of error lines connected to the data source port.

The error width must be set to at least floor(log2(maximum error)) + 1.

Note: Applicable only when parameter Error Enable is enabled.
74 Modular SGDMA dispatcher module must have extended features enabled.
Level Two Title