1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
1.1. SEU Mitigation Techniques
The Intel® Quartus® Prime software offers several features to detect, correct, and characterize the effects of SEU on your designs. Additionally, Intel Agilex® 7 FPGAs contain dedicated circuitry to help detect and correct errors.
Intel Agilex® 7 SEU mitigation features can benefit the system by:
- Ensuring the system functions properly at all time
- Preventing a system malfunction caused by an SEU event
- Handling the SEU event if it is critical to the system
|Area||SEU Mitigation Approach|
|Error detection and correction||Enable the error detection and correction (EDC) feature to detect CRAM SEU events and automatically correct the CRAM contents.|
|Memory block error correction code||Take advantage of the error correction code (ECC) feature and the special layout design of the Intel Agilex® 7 M20K memory blocks to reduce SEU failures in time (FIT) rate to almost zero.|
|SEU sensitivity processing||Use the sensitivity processing feature to identify if the SEU on a CRAM bit location is critical to the function of your compiled FPGA design bitstream file.|
Use the fault injection feature to help you validate system response to the SEU event by intentionally changing the CRAM state to trigger an error.
Intel Agilex® 7 supports ECC error injection to M20K blocks.
|Hierarchy tagging||Use hierarchy tagging, together with sensitivity processing and fault injection, to report SEU and constrain error injection to specific portions of your design logic.|
|Triple modular redundancy||Use triple modular redundancy (TMR) technique on critical logic such as state machines to improve hardware fault tolerance.|
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