1.1. SEU Mitigation Techniques
Intel Agilex® 7 SEU mitigation features can benefit the system by:
- Ensuring the system functions properly at all time
- Preventing a system malfunction caused by an SEU event
- Handling the SEU event if it is critical to the system
|Area||SEU Mitigation Approach|
|Error detection and correction||Enable the error detection and correction (EDC) feature to detect CRAM SEU events and automatically correct the CRAM contents.|
|Memory block error correction code||Take advantage of the error correction code (ECC) feature and the special layout design of the Intel Agilex® 7 M20K memory blocks to reduce SEU failures in time (FIT) rate to almost zero.|
|SEU sensitivity processing||Use the sensitivity processing feature to identify if the SEU on a CRAM bit location is critical to the function of your compiled FPGA design bitstream file.|
Use the fault injection feature to help you validate system response to the SEU event by intentionally changing the CRAM state to trigger an error.
Intel Agilex® 7 supports ECC error injection to M20K blocks.
|Hierarchy tagging||Use hierarchy tagging, together with sensitivity processing and fault injection, to report SEU and constrain error injection to specific portions of your design logic.|
|Triple modular redundancy||Use triple modular redundancy (TMR) technique on critical logic such as state machines to improve hardware fault tolerance.|
Did you find the information on this page useful?