Intel Agilex® 7 SEU Mitigation User Guide

ID 683128
Date 4/10/2023
Document Table of Contents

2.4.1. Advanced SEU Detection Intel® FPGA IP

The Advanced SEU Detection Intel® FPGA IP allows you to perform runtime on-chip and off-chip lookup sensitivity processing for SEU errors.
  • On-chip—the sensitivity processing soft IP provides error location reporting and lookup.
  • Off-chip—an external unit such as a microprocessor performs error location lookup using information from the error message queue.

The Advanced SEU Detection IP does the following:

  • Communicates with the secure device manager (SDM) to detect SEU event by sending commands and receiving responses for SEU error reports.
  • Read sensitivity map header (.smh) file to allow on-chip or off-chip lookup sensitivity processing, and report criticality of SEU error occurrence in device based on the specified regions in the file.
Note: You cannot simulate the Advanced SEU Detection IP because the IP receives the response from SDM. To validate this IP core, Intel recommends that you perform hardware evaluation.

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