1.3. Memory Blocks
The eSRAM blocks are only available in selected Intel Agilex® 7 devices. Refer to the Intel Agilex® 7 FPGA and SoCs Device Overview to determine which devices contain eSRAM blocks. The M20K blocks and eSRAM blocks support ECC. The ECC feature detects and corrects data errors at the output of the memory.
|Item||M20K Block||eSRAM Block|
|Built-in support||In ×32-wide simple dual-port mode||In ×64-wide simple dual-port mode.|
32-bit word error detection and correction:
The ECC cannot guarantee detection or correction of non-adjacent two-bit (or more) errors.
64-bit word error detection or correction:
|Flags indicating memory status||
The status flags are part of the regular outputs from the memory block.
When you engage ECC, the M20K memory runs slower than in non-ECC simple dual-port mode. To achieve a higher performance—compared to non-pipeline ECC mode—at the expense of a one-cycle latency, enable the optional ECC pipeline registers before the output decoder.
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