1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
5. IP and Software References
The SEU mitigation features of the Intel Agilex® 7 device provide you tools to configure, analyze, and simulate SEU errors.
- Advanced SEU Detection Intel® FPGA IP—allows you to perform runtime on-chip and off-chip lookup sensitivity processing for SEU errors.
- Fault Injection Debugger—injects random CRAM bit flips into the FPGA during system operation to simulate SEU strikes for testing, debugging, and refining your design's SEU detection and recovery sequence.
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