1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
1. Intel Agilex® 7 SEU Mitigation Overview
|Intel® Quartus® Prime Design Suite 23.1|
Single event upsets (SEUs) are rare and unintended changes in the internal memory elements of an FPGA caused by cosmic radiation. The memory state change is a soft error with no permanent damage but the FPGA may operate erroneously until background scrubbing fixes the upset.
Because of the low chance of occurrence, your design may not require SEU mitigation. However, if your system includes multiple FPGAs and requires very high reliability and availability, consider using mitigation techniques to detect and recover from SEU errors.
SEU Mitigation Techniques
Secure Device Manager ECC and SmartVID
Triple Modular Redundancy
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