184.108.40.206. Step 4: Customize Delay Calibration
one_ms_delay = 1000
If this parameter is known, adjust it accordingly. Otherwise, use code similar to the code included for Windows and DOS platforms that counts the number of clock cycles it takes to execute a single loop. This code has been sampled over multiple tests and, on average, produces an accurate delay result. The advantage to this approach is that calibration can vary based on the speed of the host processor.
After the Jam STAPL Byte-Code Player is ported and working, verify the timing and speed of the JTAG port at the target device. Timing parameters for the supported Altera devices must comply with the JTAG timing parameters and values provided in the data sheet of the relevant device family.
If the Jam STAPL Byte-Code Player does not operate within the timing specifications, you must optimize the code with the appropriate delays. Timing violations can occur in powerful processors that can generate TCK at a rate faster than 10 MHz.
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