184.108.40.206. Connecting the JTAG Chain to an Existing Bus Using an Interface Device
Design Schematic of Interface Device
The following figure shows an example design schematic of an interface device. This example design is for your reference only. If you use this example, you must ensure that:
- TMS, TCK, and TDI are synchronous outputs
- Multiplexer logic is included to allow board access for the MasterBlaster or ByteBlasterMV download cable
The embedded processor asserts the JTAG chain’s address. You can set the R_nW and R_AS signals to notify the interface device when you want the processor to access the chain.
- To write—connect the data[3..0] data path to the JTAG outputs of the device using the three D registers that are clocked by the system clock (CLK). This clock can be the same clock used by the processor.
- To read—enable the tri-state buffers and let the TDO signal flow back to the processor.
This example design also provides a hardware connection to read back the values in the TDI, TMS, and TCK registers. This optional feature is useful during the development phase because it allows the software to check the valid states of the registers in the interface device.
In addition, the example design includes multiplexer logic to permit a MasterBlaster or ByteBlasterMV download cable to program the device chain. This capability is useful during the prototype phase of development when you want to verify the programming and configuration.
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