AN 425: Using the Command-Line Jam STAPL Solution for Device Programming

ID 683089
Date 12/09/2016
Public
Document Table of Contents

1.5.1.2. Connecting the JTAG Chain to an Existing Bus Using an Interface Device

In this method, the JTAG chain is represented by an address on the existing bus and the processor performs read and write operations on this address.
Figure 8. Connecting the JTAG Chain to the Embedded System


Design Schematic of Interface Device

The following figure shows an example design schematic of an interface device. This example design is for your reference only. If you use this example, you must ensure that:

  • TMS, TCK, and TDI are synchronous outputs
  • Multiplexer logic is included to allow board access for the MasterBlaster or ByteBlasterMV download cable
Figure 9. Interface Logic Design ExampleExcept for the data[3..0] data path, all other inputs in this figure are optional. These inputs are included only to illustrate how you can use the interface device as an address on an embedded data bus.


The embedded processor asserts the JTAG chain’s address. You can set the R_nW and R_AS signals to notify the interface device when you want the processor to access the chain.

  • To write—connect the data[3..0] data path to the JTAG outputs of the device using the three D registers that are clocked by the system clock (CLK). This clock can be the same clock used by the processor.
  • To read—enable the tri-state buffers and let the TDO signal flow back to the processor.

This example design also provides a hardware connection to read back the values in the TDI, TMS, and TCK registers. This optional feature is useful during the development phase because it allows the software to check the valid states of the registers in the interface device.

In addition, the example design includes multiplexer logic to permit a MasterBlaster or ByteBlasterMV download cable to program the device chain. This capability is useful during the prototype phase of development when you want to verify the programming and configuration.