Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation
ID
683080
Date
2/05/2024
Public
1.1. Intel FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Types
1.5. Supported Simulation Flows
1.6. Supported Hardware Description Languages
1.7. Supported Simulators
1.8. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.9. Intel FPGA Simulation Basics Revision History
1.3.3.2. Running the Simulation Library Compiler in a Terminal
You can run the Intel® Quartus® Prime Simulation Library Compiler in a terminal without launching the Intel® Quartus® Prime software GUI.
The following example command generates the Questasim compile.do simulation script that compiles all Verilog HDL simulation files for the specified device family.
quartus_sh –simlib_comp -family cyclonev -tool questasim \ -language verilog -gen_only -cmd_file compile.do
To view all available command-line options, you can run the following command:
quartus_sh --help=simlib_comp