Visible to Intel only — GUID: mwh1410383451815
Ixiasoft
Visible to Intel only — GUID: mwh1410383451815
Ixiasoft
2.2.3. Passing Parameter Information from Verilog HDL to VHDL
By default, the x_on_violation_option logic option is enabled for all design registers, resulting in an output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register, disable the x_on_violation_option logic option for the specific register, as shown in the following example from the Intel® Quartus® Prime Settings File (.qsf).
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name>
In-line Parameter Passing Example
lpm_add_sub#(.lpm_width(12), .lpm_direction("Add"),
.lpm_type("LPM_ADD_SUB"),
.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" ))
lpm_add_sub_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0)
);
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