Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 9/24/2018

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2.2.3. Passing Parameter Information from Verilog HDL to VHDL

You must use in-line parameters to pass values from Verilog HDL to VHDL.

By default, the x_on_violation_option logic option is enabled for all design registers, resulting in an output of “X” at timing violation. To disable “X” propagation at timing violations on a specific register, disable the x_on_violation_option logic option for the specific register, as shown in the following example from the Intel® Quartus® Prime Settings File (.qsf).

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \ <register_name>

In-line Parameter Passing Example

lpm_add_sub#(.lpm_width(12), .lpm_direction("Add"),

lpm_add_sub_component (
        .dataa (dataa),
        .datab (datab),
        .result (sub_wire0)
Note: The sequence of the parameters depends on the sequence of the GENERIC in the VHDL component declaration.