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1.1. Simulator Support 1.2. Simulation Levels 1.3. HDL Support 1.4. Simulation Flows 1.5. Preparing for Simulation 1.6. Simulating Intel® FPGA IP Cores 1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.8. Running a Simulation (Custom Flow) 1.9. Simulating Intel FPGA Designs Revision History
2.2.1. Using ModelSim-Intel FPGA Edition Precompiled Libraries 2.2.2. Disabling Timing Violation on Registers 2.2.3. Passing Parameter Information from Verilog HDL to VHDL 2.2.4. Increasing Simulation Speed 2.2.5. Simulating Transport Delays 2.2.6. Viewing Simulation Messages 2.2.7. Generating Power Analysis Files 2.2.8. Viewing Simulation Waveforms 2.2.9. Simulating with ModelSim-Intel FPGA Edition Waveform Editor
2.1. Quick Start Example (ModelSim with Verilog)
You can adapt the following RTL simulation example to get started quickly with ModelSim:
- To specify your EDA simulator and executable path, type the following Tcl package command in the Intel® Quartus® Prime tcl shell window:
set_user_option -name EDA_TOOL_PATH_MODELSIM <modelsim executable path>set_global_assignment -name EDA_SIMULATION_TOOL "MODELSIM (verilog)"
- Compile simulation model libraries using one of the following methods:
- Run NativeLink RTL simulation to compile required design files, simulation models, and run your simulator. Verify results in your simulator. If you complete this step you can ignore the remaining steps.
- To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
- Type the following commands to create and map Intel FPGA simulation libraries manually, and then compile the models manually:
vlib <lib1>_ver vmap <lib1>_ver <lib1>_ver vlog -work <lib1> <lib1>
Use the compiled simulation model libraries during simulatation of your design. Refer to your EDA simulator's documentation for information about running simulation.
- Compile your design and testbench files:
vlog -work work <design or testbench name>.v
- Load the design:
vsim -L work -L <lib1>_ver -L <lib2>_ver work.<testbench name>
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