Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 9/24/2018
Public

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2.2.7. Generating Power Analysis Files

To generate a timing Value Change Dump File (.vcd) for power analysis, you must first generate a <filename>_dump_all_vcd_nodes.tcl script file in the Intel® Quartus® Prime software. You can then run the script from the ModelSim, QuestaSim, or ModelSim-Intel FPGA Edition software to generate a timing .vcd for use in the Intel® Quartus® Prime power analyzer.

To generate and use a .vcd for power analysis, follow these steps:

  1. In the Intel® Quartus® Prime software, click Assignments > Settings.
  2. Under EDA Tool Settings, click Simulation.
  3. Turn on Generate Value Change Dump file script, specify the type of output signals to include, and specify the top-level design instance name in your testbench. For example, if your top level design name is Top, and your testbench wrapper calls Top as instance Top_inst, specify the top level design instance name as Top_inst.
  4. Click Processing > Start Compilation. The Compiler creates the <filename>_dump_all_vcd_nodes.tcl file, the ModelSim simulation <filename>_run_msim_gate_vhdl/verilog.do file (including the .vcd and .tcl execution lines). Use the <filename>_dump_all_vcd_nodes.tcl to dump all of the signals that you expect for input back into the Power Analysis.
  5. Elaborate and compile the design in your simulator.
  6. Source the <filename>_run_msim_gate_vhdl/verilog.do file, and then run the simulation. The simulator opens the .vcd file that contains the dumped signal file transition information.
  7. Stop the simulation if your testbench does not have a break point.