Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 9/24/2018

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1.5.1. Compiling Simulation Models

The Intel® Quartus® Prime software includes simulation models for all Intel FPGA IP cores. These models include IP functional simulation models, and device family-specific models in the < Intel® Quartus® Prime installation path>/eda/sim_lib directory. These models include IEEE encrypted Verilog HDL models for both Verilog HDL and VHDL simulation.

Before running simulation, you must compile the appropriate simulation models from the Intel® Quartus® Prime simulation libraries using any of the following methods:

  • Use the NativeLink feature to automatically compile your design, Intel FPGA IP, simulation model libraries, and testbench.
  • To automatically compile all required simulation model libraries for your design in your supported simulator, click Tools > Launch Simulation Library Compiler. Specify options for your simulation tool, language, target device family, and output location, and then click OK.
  • Compile Intel® Quartus® Prime simulation models manually with your simulator.

Use the compiled simulation model libraries to simulate your design. Refer to your EDA simulator's documentation for information about running simulation.

Note: The specified timescale precision must be within 1ps when using Intel® Quartus® Prime simulation models.