1.1. Simulator Support 1.2. Simulation Levels 1.3. HDL Support 1.4. Simulation Flows 1.5. Preparing for Simulation 1.6. Simulating Intel® FPGA IP Cores 1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.8. Running a Simulation (Custom Flow) 1.9. Simulating Intel FPGA Designs Revision History
2.2.1. Using ModelSim-Intel FPGA Edition Precompiled Libraries 2.2.2. Disabling Timing Violation on Registers 2.2.3. Passing Parameter Information from Verilog HDL to VHDL 2.2.4. Increasing Simulation Speed 2.2.5. Simulating Transport Delays 2.2.6. Viewing Simulation Messages 2.2.7. Generating Power Analysis Files 2.2.8. Viewing Simulation Waveforms 2.2.9. Simulating with ModelSim-Intel FPGA Edition Waveform Editor
3.2.1. Simulating Transport Delays
By default, the VCS and VCS MX software filter out all pulses that are shorter than the propagation delay between primitives. Turning on the transport delay options in the VCS and VCS MX software prevents the simulator from filtering out these pulses. Intel® Arria® 10 devices do not support timing simulation.
|+transport_path_delays||Use when simulation pulses are shorter than the delay in a gate-level primitive. You must include the +pulse_e/number and +pulse_r/number options.|
|+transport_int_delays||Use when simulation pulses are shorter than the interconnect delay between gate-level primitives. You must include the +pulse_int_e/number and +pulse_int_r/number options.|
Note: The +transport_path_delays and +transport_path_delays options apply automatically during NativeLink gate-level timing simulation.
The following VCS and VCS MX software command runs a post-synthesis simulation:
vcs -R <testbench>.v <gate-level netlist>.v -v <Intel FPGA device family \ library>.v +transport_int_delays +pulse_int_e/0 +pulse_int_r/0 \ +transport_path_delays +pulse_e/0 +pulse_r/0
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