Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation
ID
683080
Date
9/24/2018
Public
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1.1. Simulator Support
1.2. Simulation Levels
1.3. HDL Support
1.4. Simulation Flows
1.5. Preparing for Simulation
1.6. Simulating Intel® FPGA IP Cores
1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.8. Running a Simulation (Custom Flow)
1.9. Simulating Intel FPGA Designs Revision History
2.2.1. Using ModelSim-Intel FPGA Edition Precompiled Libraries
2.2.2. Disabling Timing Violation on Registers
2.2.3. Passing Parameter Information from Verilog HDL to VHDL
2.2.4. Increasing Simulation Speed
2.2.5. Simulating Transport Delays
2.2.6. Viewing Simulation Messages
2.2.7. Generating Power Analysis Files
2.2.8. Viewing Simulation Waveforms
2.2.9. Simulating with ModelSim-Intel FPGA Edition Waveform Editor
1.2. Simulation Levels
The Intel® Quartus® Prime software supports RTL and gate-level simulation of IP cores in supported EDA simulators.
Simulation Level | Description | Simulation Input |
---|---|---|
RTL | Cycle-accurate simulation using Verilog HDL, SystemVerilog, and VHDL design source code with simulation models provided by Intel and other IP providers. |
|
Gate-level functional | Simulation using a post-synthesis or post-fit functional netlist testing the post-synthesis functional netlist, or post-fit functional netlist. |
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Gate-level timing | Simulation using a post-fit timing netlist, testing functional and timing performance. Supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families. |
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Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.. Use Timing Analyzer static timing analysis rather than gate-level timing simulation.