Quad-Serial Configuration (EPCQ) Devices Datasheet

ID 683078
Date 1/23/2020
Document Table of Contents

1.7.2. Write Enable Operation (06h)

When you enable the write enable operation, the write enable latch bit is set to 1 in the status register. You must execute this operation before the write bytes, write status, erase bulk, erase sector, extended dual input fast write bytes, extended quad input fast write bytes, 4BYTEADDREN, and 4BYTEADDREX operations.

Figure 8. Write Enable Operation Timing Diagram