Quad-Serial Configuration (EPCQ) Devices Datasheet

ID 683078
Date 1/23/2020
Public
Document Table of Contents
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1.7.3. Write Disable Operation (04h)

The write disable operation resets the write enable latch bit in the status register. To prevent the memory from being written unintentionally, the write enable latch bit is automatically reset when implementing the write disable operation, and under the following conditions:

  • Power up
  • Write bytes operation completion
  • Write status operation completion
  • Erase bulk operation completion
  • Erase sector operation completion
  • Extended dual input fast write bytes operation completion
  • Extended quad input fast write bytes operation completion
Figure 9. Write Disable Operation Timing Diagram