Quad-Serial Configuration (EPCQ) Devices Datasheet

Download PDF
ID 683078
Date 1/23/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
1. Quad-Serial Configuration (EPCQ) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Operating Conditions 1.4. Memory Array Organization 1.5. Memory Operations 1.6. Registers 1.7. Summary of Operation Codes 1.8. Power Mode 1.9. Timing Information 1.10. Programming and Configuration File Support 1.11. Pin Information 1.12. Device Package and Ordering Code 1.13. Document Revision History for Quad-Serial Configuration (EPCQ) Devices Datasheet
1.3. Operating Conditions x
1.3.1. Absolute Maximum Ratings 1.3.2. Recommended Operating Conditions 1.3.3. DC Operating Conditions 1.3.4. ICC Supply Current 1.3.5. Capacitance
1.4. Memory Array Organization x
1.4.1. Address Range for EPCQ16 1.4.2. Address Range for EPCQ32 1.4.3. Address Range for EPCQ64 1.4.4. Address Range for EPCQ128 1.4.5. Address Range for EPCQ256 1.4.6. Address Range for EPCQ512/A
1.5. Memory Operations x
1.5.1. Timing Requirements 1.5.2. Addressing Mode
1.6. Registers x
1.6.1. Status Register 1.6.2. Flag Status Register 1.6.3. Non-Volatile Configuration Register
1.6.1. Status Register x
1.6.1.1. Read Status Register Operation (05h) 1.6.1.2. Write Status Register Operation (01h)
1.6.1.1. Read Status Register Operation (05h) x
1.6.1.1.1. Block Protection Bits in EPCQ16 when TB Bit is Set to 0 1.6.1.1.2. Block Protection Bits in EPCQ16 when TB Bit is Set to 1 1.6.1.1.3. Block Protection Bits in EPCQ32 when TB Bit is Set to 0 1.6.1.1.4. Block Protection Bits in EPCQ32 when TB Bit is Set to 1 1.6.1.1.5. Block Protection Bits in EPCQ64 when TB Bit is Set to 0 1.6.1.1.6. Block Protection Bits in EPCQ64 when TB Bit is Set to 1 1.6.1.1.7. Block Protection Bits in EPCQ128 when TB Bit is Set to 0 1.6.1.1.8. Block Protection Bits in EPCQ128 when TB Bit is Set to 1 1.6.1.1.9. Block Protection Bits in EPCQ256 when TB Bit is Set to 0 1.6.1.1.10. Block Protection Bits in EPCQ256 when TB Bit is Set to 1 1.6.1.1.11. Block Protection Bits in EPCQ512/A when TB is Set to 0 1.6.1.1.12. Block Protection Bits in EPCQ512/A when TB is Set to 1
1.6.2. Flag Status Register x
1.6.2.1. Read Flag Status Register Operation(70h)
1.6.3. Non-Volatile Configuration Register x
1.6.3.1. Read Non-Volatile Configuration Register Operation (B5h) 1.6.3.2. Write Non-Volatile Configuration Register Operation (B1h)
1.7. Summary of Operation Codes x
1.7.1. 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) 1.7.2. Write Enable Operation (06h) 1.7.3. Write Disable Operation (04h) 1.7.4. Read Bytes Operation (03h) 1.7.5. Fast Read Operation (0Bh) 1.7.6. Extended Dual Input Fast Read Operation (BBh) 1.7.7. Extended Quad Input Fast Read Operation (EBh) 1.7.8. Read Device Identification Operation (9Fh) 1.7.9. Write Bytes Operation (02h) 1.7.10. Extended Dual Input Fast Write Bytes Operation (D2h) 1.7.11. Extended Quad Input Fast Write Bytes Operation (12h or 38h) 1.7.12. Erase Bulk Operation (C7h) 1.7.13. Erase Sector Operation (D8h) 1.7.14. Erase Subsector Operation
1.9. Timing Information x
1.9.1. Write Operation Timing 1.9.2. Read Operation Timing
1.11. Pin Information x
1.11.1. Pin-Out Diagram for EPCQ16 and EPCQ32 Devices 1.11.2. Pin-Out Diagram for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices 1.11.3. EPCQ Device Pin Description
1.12. Device Package and Ordering Code x
1.12.1. Package 1.12.2. Ordering Code
1. Quad-Serial Configuration (EPCQ) Devices Datasheet

1.13. Document Revision History for Quad-Serial Configuration (EPCQ) Devices Datasheet

Document Version Changes
2020.01.23 Updated the Read Device Identification Operation Timing Diagram.
2018.06.01
  • Updated the description for tDSU parameter.
  • Added data retention feature information.
  • Added information about the read flag status register operation.
  • Added a note to Absolute Maximum Ratings to state the maximum undershoot and overshoot for VI.
  • Updated the product obsolescence note in Supported Intel EPCQ Devices table.
  • Added a link to PDN1802.
Date Version Changes
November 2017 2017.11.06
  • Updated operation code from binary to hexadecimal value in Summary of Operation Codes table.
  • Added operation code in hex value in each operation timing diagrams.
  • Updated operation timing diagrams to improve operation code and DLCK alignment accuracy.
  • Added Registers section and included read status, write status, read non-volatile configuration, and read non-volatile configuration registers.
  • Added note stating EPCQ16, EPCQ32, EPCQ64, and EPCQ128 are scheduled for product obsolescence.
  • Added Extended Quad Input Fast Write Bytes Operation Timing Diagram for EPCQ512/A figure.
  • Added extended quad input fast write bytes operation code for EPCQ512/A in Summary of Operation Codes table.
  • Removed ambient temperature in Absolute Maximum Ratings.
  • Added note to EPCQ512/A device is shown as EPCQ512 in Intel® Quartus® Prime software.
  • Updated Write Operation Timing for EPCQ512/A devices.
  • Updated Recommended Operating Conditions and ICC Supply Current for EPCQ512/A devices.
  • Updated capacitance is sample-tested at a 54 MHz frequency.
May 2016 2016.05.30
  • Removed instances of 'Preliminary' and notes about pending characterization.
  • Replaced EPCQ512 instances with EPCQ512/A.
  • Updated ordering code for EPCQ512/A.
  • Updated AS x1 and AS x4 Pin-Out Diagrams for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices figure.
  • Updated Power dissipation and Joint temperature in the Absolute Maximum Ratings table.
January 2015 2015.01.23
  • Updated non-volatile configuration register operation code.
  • Added erase subsector operation.
  • Added read non-volatile configuration register operation.
  • Updated AS x1 dummy clock cycles for non-volatile configuration registers.
  • Updated the erase and program cycle to up to 100,000 cycles.
  • Updated write non-volatile configuration register 16-bit register value.
  • Added Non-volatile Configuration Register Operation Bit Definition table.
  • Added read status operation timing diagram.
  • Updated EPCQ Device Pin Description table.
  • Added a link to the Packaging Specifications and Dimensions page.
January 2014 2014.01.10
  • Added EPCQ512 device support.
  • Added the write non-volatile configuration register operation.
  • Added a link to the ALTASMI_PARALLEL IP Core User Guide.
  • Removed preliminary for EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256 devices.
  • Updated block protection bits for EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256 devices.
  • Updated the dummy byte term to dummy cycle.
  • Updated the dummy cycles for the read device identification operation in the Operation Codes for EPCQ Devices.
  • Updated the tCL and tCH parameters in the write operation timing diagram.
  • Updated the Package section.
  • Updated the erase bulk cycle time for EPCQ16 and EPCQ32 devices.
  • Updated the operating temperature in the Recommended Operating Conditions.
July 2012 3.0
  • Added Table 3, Table 4, and Table 5 to include the address range for EPCQ16, EPCQ32, and EPCQ64 devices.
  • Added Table 9, Table 10, Table 11, Table 12, Table 13, and Table 14 to include the block protection bits for EPCQ16, EPCQ32, and EPCQ64 devices.
  • Added Figure 5, Figure 20 and Figure 21 to include EPCQ16 and EPCQ32 devices.
  • Updated the “Device Package and Ordering Code” section.
  • Updated Table 1, Table 2, Table 19, Table 20, Table 27, and Table 28 to include EPCQ16, EPCQ32, and EPCQ64 devices.
  • Updated the address bytes for the extended quad input fast write bytes operation in Table 8.
  • Updated Figure 22 and Figure 23 to include EPCQ64 devices.
January 2012 2.0
  • Added Figure 2.
  • Updated “Read Bytes Operation” and “Fast Read Operation” sections.
  • Updated Figure 1, Figure 3, Figure 4, Figure 7, and Figure 13.
  • Updated Table 5, Table 11, Table 12, and Table 14.
  • Minor text edits.
June 2011 1.0 Initial release.
Level Two Title