Quad-Serial Configuration (EPCQ) Devices Datasheet

ID 683078
Date 1/23/2020
Public
Document Table of Contents
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1.13. Document Revision History for Quad-Serial Configuration (EPCQ) Devices Datasheet

Document Version Changes
2020.01.23 Updated the Read Device Identification Operation Timing Diagram.
2018.06.01
  • Updated the description for tDSU parameter.
  • Added data retention feature information.
  • Added information about the read flag status register operation.
  • Added a note to Absolute Maximum Ratings to state the maximum undershoot and overshoot for VI.
  • Updated the product obsolescence note in Supported Intel EPCQ Devices table.
  • Added a link to PDN1802.
Date Version Changes
November 2017 2017.11.06
  • Updated operation code from binary to hexadecimal value in Summary of Operation Codes table.
  • Added operation code in hex value in each operation timing diagrams.
  • Updated operation timing diagrams to improve operation code and DLCK alignment accuracy.
  • Added Registers section and included read status, write status, read non-volatile configuration, and read non-volatile configuration registers.
  • Added note stating EPCQ16, EPCQ32, EPCQ64, and EPCQ128 are scheduled for product obsolescence.
  • Added Extended Quad Input Fast Write Bytes Operation Timing Diagram for EPCQ512/A figure.
  • Added extended quad input fast write bytes operation code for EPCQ512/A in Summary of Operation Codes table.
  • Removed ambient temperature in Absolute Maximum Ratings.
  • Added note to EPCQ512/A device is shown as EPCQ512 in Intel® Quartus® Prime software.
  • Updated Write Operation Timing for EPCQ512/A devices.
  • Updated Recommended Operating Conditions and ICC Supply Current for EPCQ512/A devices.
  • Updated capacitance is sample-tested at a 54 MHz frequency.
May 2016 2016.05.30
  • Removed instances of 'Preliminary' and notes about pending characterization.
  • Replaced EPCQ512 instances with EPCQ512/A.
  • Updated ordering code for EPCQ512/A.
  • Updated AS x1 and AS x4 Pin-Out Diagrams for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices figure.
  • Updated Power dissipation and Joint temperature in the Absolute Maximum Ratings table.
January 2015 2015.01.23
  • Updated non-volatile configuration register operation code.
  • Added erase subsector operation.
  • Added read non-volatile configuration register operation.
  • Updated AS x1 dummy clock cycles for non-volatile configuration registers.
  • Updated the erase and program cycle to up to 100,000 cycles.
  • Updated write non-volatile configuration register 16-bit register value.
  • Added Non-volatile Configuration Register Operation Bit Definition table.
  • Added read status operation timing diagram.
  • Updated EPCQ Device Pin Description table.
  • Added a link to the Packaging Specifications and Dimensions page.
January 2014 2014.01.10
  • Added EPCQ512 device support.
  • Added the write non-volatile configuration register operation.
  • Added a link to the ALTASMI_PARALLEL IP Core User Guide.
  • Removed preliminary for EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256 devices.
  • Updated block protection bits for EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256 devices.
  • Updated the dummy byte term to dummy cycle.
  • Updated the dummy cycles for the read device identification operation in the Operation Codes for EPCQ Devices.
  • Updated the tCL and tCH parameters in the write operation timing diagram.
  • Updated the Package section.
  • Updated the erase bulk cycle time for EPCQ16 and EPCQ32 devices.
  • Updated the operating temperature in the Recommended Operating Conditions.
July 2012 3.0
  • Added Table 3, Table 4, and Table 5 to include the address range for EPCQ16, EPCQ32, and EPCQ64 devices.
  • Added Table 9, Table 10, Table 11, Table 12, Table 13, and Table 14 to include the block protection bits for EPCQ16, EPCQ32, and EPCQ64 devices.
  • Added Figure 5, Figure 20 and Figure 21 to include EPCQ16 and EPCQ32 devices.
  • Updated the “Device Package and Ordering Code” section.
  • Updated Table 1, Table 2, Table 19, Table 20, Table 27, and Table 28 to include EPCQ16, EPCQ32, and EPCQ64 devices.
  • Updated the address bytes for the extended quad input fast write bytes operation in Table 8.
  • Updated Figure 22 and Figure 23 to include EPCQ64 devices.
January 2012 2.0
  • Added Figure 2.
  • Updated “Read Bytes Operation” and “Fast Read Operation” sections.
  • Updated Figure 1, Figure 3, Figure 4, Figure 7, and Figure 13.
  • Updated Table 5, Table 11, Table 12, and Table 14.
  • Minor text edits.
June 2011 1.0 Initial release.