Quad-Serial Configuration (EPCQ) Devices Datasheet

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ID 683078
Date 1/23/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
1. Quad-Serial Configuration (EPCQ) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Operating Conditions 1.4. Memory Array Organization 1.5. Memory Operations 1.6. Registers 1.7. Summary of Operation Codes 1.8. Power Mode 1.9. Timing Information 1.10. Programming and Configuration File Support 1.11. Pin Information 1.12. Device Package and Ordering Code 1.13. Document Revision History for Quad-Serial Configuration (EPCQ) Devices Datasheet
1.3. Operating Conditions x
1.3.1. Absolute Maximum Ratings 1.3.2. Recommended Operating Conditions 1.3.3. DC Operating Conditions 1.3.4. ICC Supply Current 1.3.5. Capacitance
1.4. Memory Array Organization x
1.4.1. Address Range for EPCQ16 1.4.2. Address Range for EPCQ32 1.4.3. Address Range for EPCQ64 1.4.4. Address Range for EPCQ128 1.4.5. Address Range for EPCQ256 1.4.6. Address Range for EPCQ512/A
1.5. Memory Operations x
1.5.1. Timing Requirements 1.5.2. Addressing Mode
1.6. Registers x
1.6.1. Status Register 1.6.2. Flag Status Register 1.6.3. Non-Volatile Configuration Register
1.6.1. Status Register x
1.6.1.1. Read Status Register Operation (05h) 1.6.1.2. Write Status Register Operation (01h)
1.6.1.1. Read Status Register Operation (05h) x
1.6.1.1.1. Block Protection Bits in EPCQ16 when TB Bit is Set to 0 1.6.1.1.2. Block Protection Bits in EPCQ16 when TB Bit is Set to 1 1.6.1.1.3. Block Protection Bits in EPCQ32 when TB Bit is Set to 0 1.6.1.1.4. Block Protection Bits in EPCQ32 when TB Bit is Set to 1 1.6.1.1.5. Block Protection Bits in EPCQ64 when TB Bit is Set to 0 1.6.1.1.6. Block Protection Bits in EPCQ64 when TB Bit is Set to 1 1.6.1.1.7. Block Protection Bits in EPCQ128 when TB Bit is Set to 0 1.6.1.1.8. Block Protection Bits in EPCQ128 when TB Bit is Set to 1 1.6.1.1.9. Block Protection Bits in EPCQ256 when TB Bit is Set to 0 1.6.1.1.10. Block Protection Bits in EPCQ256 when TB Bit is Set to 1 1.6.1.1.11. Block Protection Bits in EPCQ512/A when TB is Set to 0 1.6.1.1.12. Block Protection Bits in EPCQ512/A when TB is Set to 1
1.6.2. Flag Status Register x
1.6.2.1. Read Flag Status Register Operation(70h)
1.6.3. Non-Volatile Configuration Register x
1.6.3.1. Read Non-Volatile Configuration Register Operation (B5h) 1.6.3.2. Write Non-Volatile Configuration Register Operation (B1h)
1.7. Summary of Operation Codes x
1.7.1. 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) 1.7.2. Write Enable Operation (06h) 1.7.3. Write Disable Operation (04h) 1.7.4. Read Bytes Operation (03h) 1.7.5. Fast Read Operation (0Bh) 1.7.6. Extended Dual Input Fast Read Operation (BBh) 1.7.7. Extended Quad Input Fast Read Operation (EBh) 1.7.8. Read Device Identification Operation (9Fh) 1.7.9. Write Bytes Operation (02h) 1.7.10. Extended Dual Input Fast Write Bytes Operation (D2h) 1.7.11. Extended Quad Input Fast Write Bytes Operation (12h or 38h) 1.7.12. Erase Bulk Operation (C7h) 1.7.13. Erase Sector Operation (D8h) 1.7.14. Erase Subsector Operation
1.9. Timing Information x
1.9.1. Write Operation Timing 1.9.2. Read Operation Timing
1.11. Pin Information x
1.11.1. Pin-Out Diagram for EPCQ16 and EPCQ32 Devices 1.11.2. Pin-Out Diagram for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices 1.11.3. EPCQ Device Pin Description
1.12. Device Package and Ordering Code x
1.12.1. Package 1.12.2. Ordering Code
1. Quad-Serial Configuration (EPCQ) Devices Datasheet

1.6.1. Status Register

Table 14.  Status Register Bits
Bit R/W Default Value Name Value Description
7 R/W 0 None
6 R/W 0 BP3 (Block Protect Bit) 9 10 Table 15 through Table 26 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally.
5 R/W 0 TB (Top/Bottom Bit)
  • 1=Protected area starts from the bottom of the memory array.
  • 0=Protected area starts from the top of the memory array.
 Determine that the protected area starts from the top or bottom of the memory array.
4 R/W 0 BP29 Table 15 through Table 26 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally.
3 BP19
2 BP09
1 R 0 WEL (Write Enable Latch Bit)
  • 1=Allows the following operation to run:
    • Write Bytes
    • Write Status Register
    • Erase Bulk
    • Erase Die
    • Erase Sector
  • 0=Rejects the above mentioned operations.
 Allows or rejects certain operation to run.
0 R 0 WIP (Write in Progress Bit)
  • 1=One of the following operation is in progress:
    • Write Status Register
    • Write NVCR
    • Write Bytes
    • Erase
  • 0=no write or erase cycle in progress
 Indicates if there is a command in progress.

Section Content
Read Status Register Operation (05h)
Write Status Register Operation (01h)

9 The erase bulk and erase die operation is only available when all the block protect bits are set to 0. When any of the block protect bits are set to 1, the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation.
10 Applicable for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A devices only.
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