Quad-Serial Configuration (EPCQ) Devices Datasheet

ID 683078
Date 1/23/2020
Document Table of Contents

1.10. Programming and Configuration File Support

The Intel® Quartus® Prime software provides programming support for EPCQ devices. When you select an EPCQ device, the Intel® Quartus® Prime software automatically generates the Programmer Object File (.pof) to program the device. The software allows you to select the appropriate EPCQ device density that most efficiently stores the configuration data for the selected FPGA.

You can program the EPCQ device in-system by an external microprocessor using the SRunner software driver. The SRunner software driver is developed for embedded EPCQ device programming that you can customize to fit in different embedded systems. The SRunner software driver reads .rpd files and writes to the EPCQ devices. The programming time is comparable to the Intel® Quartus® Prime software programming time. Because the FPGA reads the LSB of the .rpd data first during the configuration process, the LSB of .rpd bytes must be shifted out first during the read bytes operation and shifted in first during the write bytes operation.

Writing and reading the .rpd file to and from the EPCQ device is different from the other data and address bytes.

During the ISP of an EPCQ device using the Intel® FPGA Download Cable Intel® FPGA Download Cable II, Intel® FPGA Ethernet Cable, the cable pulls the nCONFIG signal low to reset the FPGA and overrides the 10-kΩ pull-down resistor on the nCE pin of the FPGA. The download cable then uses the interface pins depending on the selected AS mode to program the EPCQ device. When programming is complete, the download cable releases the interface pins of the EPCQ device and the nCE pin of the FPGA and pulses the nCONFIG signal to start the configuration process.

The FPGA can program the EPCQ device in-system using the JTAG interface with the SFL. This solution allows you to indirectly program the EPCQ device using the same JTAG interface that is used to configure the FPGA.