AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

ID 683077
Date 2/06/2020
Document Table of Contents

Migrating the RX Multi-Link Design from Simulation to Synthesis

Steps to prepare for the simulation to synthesis design migration.
  1. Make a copy of the models folder. This folder is the working folder to migrate the multi-link design from simulation to synthesis.
  2. Copy the following files and folder from the ed_sim/testbench folder into the working folder for migration:
    • pattern
    • transport_layer
    • spi_3wire.v
    • spi_mosi_oe.v
    • switch_debouncer.v
  3. Copy the following folders and files from the ed_synth folder into the working folder for migration:
    • system_console
    • altera_jesd204_ed_RX.qpf
    • altera_jesd204_ed_RX.qsf
    • altera_jesd204_ed_RX_assignment_defaults.qdf
    • altera_jesd204_ed_RX.sdc