AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

ID 683077
Date 2/06/2020
Document Table of Contents

ADC- Intel® Arria® 10 Multi-Link Design Overview

The design example Platform Designer system and top-level HDL file are designed for easy implementation of a JESD204B multi-link use case. In the top-level HDL file, each link in a JESD204B multi-link use case corresponds to an instantiation of a JESD204B IP core, a RX transport layer and a pattern checker​. Multi-link design is created by adding multiple JESD204B IP cores, transport layers and pattern checkers to the single link design example. The LINK parameter at the top-level HDL generates multiple transport layers and checkers. You must duplicate JESD204B IP cores in Platform Designer and make connections to the transport layers and pattern checkers. For synchronized multi-link, AND gates are used to combine the synchronization and alignment signals. This section assumes that each RX transport layer and pattern checker in the multi-link design have identical parameter configurations.

Figure 1.  Platform Designer System of the Design Example

The altera_jesd204_subsystem_RX Platform Designer subsystem contains one RX IP core to interface with one ADC. To interface with multiple synchronized converters, the altera_jesd204_subsystem_RX Platform Designer subsystem should contain multiple IP cores. To interface with multiple unsynchronized converters, you need to instantiate multiple altera_jesd204_subsystem_RX Platform Designer subsystems, with each subsystem containing one IP core.