AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

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ID 683077
Date 2/06/2020
Public
Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core x
ADC- Intel® Arria® 10 Multi-Link Design Overview ADC- Intel® Arria® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Arria® 10 Multi-Link Unsynchronized ADC- Intel® Arria® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

Compiling the Design in Intel® Quartus® Prime Software

After modifying the Platform Designer system, top-level HDL file and top-level SDC constraint file, compile the design with the Intel® Quartus® Prime software. Intel® recommends that you perform Analysis and Synthesis and use the RTL Viewer to check the correctness of the connections before fully compile your multi-link design.

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