AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

ID 683077
Date 2/06/2020
Document Table of Contents

Compiling the Design in Intel® Quartus® Prime Software

After modifying the Platform Designer system, top-level HDL file and top-level SDC constraint file, compile the design with the Intel® Quartus® Prime software. Intel® recommends that you perform Analysis and Synthesis and use the RTL Viewer to check the correctness of the connections before fully compile your multi-link design.

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