AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

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ID 683077
Date 2/06/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core x
ADC- Intel® Arria® 10 Multi-Link Design Overview ADC- Intel® Arria® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Arria® 10 Multi-Link Unsynchronized ADC- Intel® Arria® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

This application note provides guidelines to scale up the single link in the JESD204B Intel FPGA IP design example generated from the Intel® Quartus® Prime software to handle multipoint link (multi-link) system. A single link in JESD204B has one or more high speed transceiver lanes or channels.

In some JESD204B applications, multiple analog-to-digital converters (ADC) and digital-to-analog converters (DAC) are used to sample or transmit independent analog signals; hence synchronization is not required. In other applications, there may be requirements to synchronize multiple converters in the array. In these applications, multiple converters interface with single logic devices, such as the Intel® Arria® 10 FPGA device. This interface is known as the multipoint link in the JESD204B specification.

Before implementing the multi-link design, you must generate the receiver (RX) single-link design example from the Intel® Quartus® Prime software. Intel® recommends that you perform an RTL simulation on this single link design example to confirm the functionality matches your expectation before transforming the design example to the multi-link design. The guidelines in the following section assume the JESD204B parameters for each link in the multi-link design are identical.


Section Content
ADC- Intel Arria 10 Multi-Link Design Overview
ADC- Intel Arria 10 Multi-Link Design Implementation Guidelines
Synchronized ADC- Intel Arria 10 Multi-Link
Unsynchronized ADC- Intel Arria 10 Multi-Link
Migrating the RX Multi-Link Design from Simulation to Synthesis
Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Arria 10 JESD204B RX IP Core

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