AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

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ID 683077
Date 2/06/2020
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Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

This application note provides guidelines to scale up the single link in the JESD204B Intel FPGA IP design example generated from the Intel® Quartus® Prime software to handle multipoint link (multi-link) system. A single link in JESD204B has one or more high speed transceiver lanes or channels.

In some JESD204B applications, multiple analog-to-digital converters (ADC) and digital-to-analog converters (DAC) are used to sample or transmit independent analog signals; hence synchronization is not required. In other applications, there may be requirements to synchronize multiple converters in the array. In these applications, multiple converters interface with single logic devices, such as the Intel® Arria® 10 FPGA device. This interface is known as the multipoint link in the JESD204B specification.

Before implementing the multi-link design, you must generate the receiver (RX) single-link design example from the Intel® Quartus® Prime software. Intel® recommends that you perform an RTL simulation on this single link design example to confirm the functionality matches your expectation before transforming the design example to the multi-link design. The guidelines in the following section assume the JESD204B parameters for each link in the multi-link design are identical.

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