AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

ID 683077
Date 2/06/2020
Document Table of Contents

Viewing the Simulation Results

The simulation testbench prints the results at the transcript or terminal where you execute the simulation script. The following example shows the printout and waveform of the simulation in ModelSim‐ Intel® FPGA Edition:

If the simulation passes, the transcript section prints TESTBENCH_PASSED: SIM PASSED! as shown in the following figure.

Figure 6. Figure 11. ModelSim‐ Intel® FPGA Edition Simulation Results Transcript

If the simulation fails, the transcript section prints TESTBENCH_FAILED: SIM FAILED! along with the failure reason.

If you want to view the waveform, the following are the explanations of a series of events during the link initialization.

  1. After the /tb_top/rst is de-asserted, the transceiver reset controller sequences the reset for the transceiver in both Link 0 and Link 1 JESD204B IP core.
  2. The /tb_top/xcvr_rst_ctrl_tx_ready is asserted when the TX transceiver channels and TX PLL are out of reset.
    Figure 7. Figure 12. ModelSim‐ Intel® FPGA Edition Simulation Waveform during Global Reset De-assertion
  3. The TX channels send data to RX channels.
  4. When the RX channels recovered the data and clock successfully, the /tb_top/xcvr_rst_ctrl_rx_ready is asserted.
  5. The reset sequencer in the Platform Designer system de-asserts the jesd204_rx_avs_rst_n so that the Avalon-MM BFM master configures the test mode CSR.
  6. The reset sequencer de-asserts the rxlink_rst_n_reset_n and the IP core is out of reset.
  7. The RX transport layer asserts the jesd204_rx_link_ready to IP core.
  8. The testbench sends a rx_sysref pulse to the IP core.
  9. The IP core de-assert the dev_sync_n.
  10. After the IP core exits the code group synchronization (CGS) phase, the IP core enters the initial lane alignment sequence (ILAS) phase.
  11. The alldev_lane_aligned is asserted when both IP cores achieve lane alignment.
  12. The jesd204_rx_link_valid is asserted when the IP core enters the user data phase and sample data is sent to RX transport layer.
  13. The RX transport layer performs the lane mapping of the sample data.
  14. The pattern checker checks the received sample data from RX transport layer.
  15. No data error is detected by the pattern checker and no interrupt is asserted by both the RX and TX IP cores.
  16. The testbench asserts the test_passed flag when the above conditions in item 15 are met.
    Figure 8. Figure 13. ModelSim‐ Intel® FPGA Edition Simulation Waveform for Successful Link Initialization