AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

ID 683077
Date 2/06/2020
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Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

Document Version Changes
2020.02.06 Reorganized the topics to separate guidelines for design simulation and design synthesis for synchronized and unsynchronized ADC multi-link designs.
2018.02.09
  • Added simulation guidelines for synchronized and unsynchronized multi-link design.
  • Added simulation to synthesis migration guidelines.
  • Added design simulation and synthesis overview.
  • Updated instances of Qsys to Platform Designer.
  • Reorganized document structure.
  • Updated document title AN803: Implementing ADC- Intel® Arria® 10 Multi-Link Design with JESD204B RX IP Core to AN803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
2017.05.08 Initial release.