F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
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4.1.4. TX MII Encoder

The TX MII encoder handles the packet transmission from the MAC to the TX PCS.

The data rate determines the TX MII pattern as shown in the following table.

Table 16.  TX MII Encoder Data Pattern
Data Rate Lane Description Pattern
1 Gb to <29 Gb 1 physical lane per 1 lane on GUI IP parameter START and END CW appear in every MII lane
29 Gb to <58 Gb 2 physical lane per 1 lane on GUI IP parameter START and END CW appear once in every two MII lanes
≥58 Gb 4 physical lane per 1 lane on GUI IP parameter START and END CW appear once in every four MII lanes

The following figures demonstrate the data pattern according to data rate.

Table 17.  TX MII Data Pattern for Data Rate of from 1 Gb to Less Than 29 Gb
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_9 DATA_17 EOP_CW
SOP_CW DATA_2 DATA_10 DATA_18 EOP_CW
SOP_CW DATA_3 DATA_11 DATA_19 EOP_CW
SOP_CW DATA_4 DATA_12 DATA_20 EOP_CW
SOP_CW DATA_5 DATA_13 DATA_21 EOP_CW
SOP_CW DATA_6 DATA_14 DATA_22 EOP_CW
SOP_CW DATA_7 DATA_15 DATA_23 EOP_CW
SOP_CW DATA_8 DATA_16 DATA_24 EOP_CW
Table 18.  TX MII Data Pattern for Data Rate of from 29 Gb to Less Than 58 Gb
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_9 DATA_17 DATA_DUMMY
DATA_DUMMY DATA_2 DATA_10 DATA_18 EOP_CW
SOP_CW DATA_3 DATA_11 DATA_19 DATA_DUMMY
DATA_DUMMY DATA_4 DATA_12 DATA_20 EOP_CW
SOP_CW DATA_5 DATA_13 DATA_21 DATA_DUMMY
DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW
SOP_CW DATA_7 DATA_15 DATA_23 DATA_DUMMY
DATA_DUMMY DATA_8 DATA_16 DATA_24 EOP_CW
Table 19.  TX MII Data Pattern for Data Rate of 58 Gb and Higher
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_9 DATA_17 DATA_DUMMY
DATA_DUMMY DATA_2 DATA_10 DATA_18 DATA_DUMMY
DATA_DUMMY DATA_3 DATA_11 DATA_19 DATA_DUMMY
DATA_DUMMY DATA_4 DATA_12 DATA_20 EOP_CW
SOP_CW DATA_5 DATA_13 DATA_21 DATA_DUMMY
DATA_DUMMY DATA_6 DATA_14 DATA_22 DATA_DUMMY
DATA_DUMMY DATA_7 DATA_15 DATA_23 DATA_DUMMY
DATA_DUMMY DATA_8 DATA_16 DATA_24 EOP_CW