F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
Document Table of Contents

6.2. Reset Signals

Table 23.  Reset Signals
Name Width Direction Clock Domain Description
tx_core_rst_n 1 Input Asynchronous Active-low reset signal.

Resets the F-Tile Serial Lite IV TX MAC.

rx_core_rst_n 1 Input Asynchronous Active-low reset signal.

Resets the F-Tile Serial Lite IV RX MAC.

tx_pcs_fec_phy_reset_n 1 Input Asynchronous Active-low reset signal.

Resets the F-Tile Serial Lite IV TX custom PCS.

rx_pcs_fec_phy_reset_n 1 Input Asynchronous Active-low reset signal.

Resets the F-Tile Serial Lite IV RX custom PCS.

reconfig_reset 1 Input reconfig_clk Active-high reset signal.

Resets the Avalon® memory-mapped interface reconfiguration block.

reconfig_sl_reset 1 Input reconfig_sl_clk Active-high reset signal.

Resets the Avalon® memory-mapped interface reconfiguration block.

tx_reset_ack 1 Output Asynchronous Active-high reset acknowledge signal.

Indicates that soft reset controller has successfully entered reset mode for TX. You can now release the tx_pcs_fec_phy_reset_n, reconfig_reset, and reconfig_sl_reset signals.

rx_reset_ack 1 Output Asynchronous Active-high reset acknowledge signal.

Indicates that soft reset controller has successfully entered reset mode for RX. You can now release the rx_pcs_fec_phy_reset_n, reconfig_reset, and reconfig_sl_reset signals.