F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
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4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture

The F-Tile Serial Lite IV Intel® FPGA IP has six clocks which generate clocks to different blocks:
  • Transceiver reference clock (xcvr_ref_clk)—Input clock from external clock chips or oscillators which generates clocks for TX PMA and RX PMA. Refer to Parameters for supported frequency range.
  • TX core clock (tx_core_clk)—This clock is derived from transceiver PLL and is used for EFIFO and TX MAC. This clock is also an output clock from the F-Tile transceiver to connect to the TX user logic.
  • RX core clock (rx_core_clk)—This clock is derived from the Clock Data Recovery (CDR) PLL and is used for EFIFO, RX deskew FIFO, and RX MAC. This clock is also an output clock from the F-Tile transceiver to connect to the RX user logic.
  • Clock for PMA reconfiguration interface (reconfig_clk)—input clock from external clock circuits or oscillators which generates clocks for F-Tile transceiver reconfiguration interface in both TX and RX PMA. The clock frequency is 100 to 162 MHz.
  • Clock for datapath reconfiguration interface (reconfig_sl_clk)—input clock from external clock circuits or oscillators which generates clocks for F-Tile transceiver reconfiguration interface in both TX and RX, PCS, FEC, and soft CSR. The clock frequency is 100 to 162 MHz.
  • System PLL clock (sysclk)—used for TX/RX EFIFO, and PCS.

The following block diagram shows F-Tile Serial Lite IV Intel® FPGA IP clock domains and the connections within the IP.

Figure 22.  F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture