F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
Document Table of Contents

4.4. Reset and Link Initialization

The MAC, F-Tile Hard IP, and reconfiguration blocks have different reset signals:
  • TX and RX MAC blocks use tx_core_rst_n and rx_core_rst_n reset signals.
  • tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n reset signals drive the soft reset controller to reset the F-Tile Hard IP.
  • Reconfiguration block uses the reconfig_reset reset signal.
Figure 23. Reset Architecture