F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
Document Table of Contents

4.6. 32-bit Soft CWBIN Counters

The F-Tile Serial Lite IV Intel® FPGA IP 32-bit soft CWBIN counters is an optional enablement for PAM4 RSFEC mode in the IP GUI Parameter Editor. The 32-bit soft CWBIN counters soft logic converts 8-bit CWBin0-3 registers in Ethernet Hard IP to 32-bit registers in soft logic. The CWBin0 register counts up when the FEC codeword receives zero errors, CWBin1 register counts up when the FEC codeword receives one error, and so on.

Only the CWBin0-3 counters are expected to increase at a high rate. As a result, this soft logic performs fast reads of these 8-bit counter values from Hard IP and accumulates these counters to 32-bit counter registers that you can access.

The F-Tile Serial Lite IV Intel® FPGA IP read rate is set to 13μs for all rates to prevent the 8-bit counters from overflowing.