F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
Document Table of Contents

4. Functional Description

F-Tile Serial Lite IV Intel® FPGA IP consists of MAC and Ethernet PCS. The MAC communicates with the custom PCS through MII interfaces.

The IP supports two modulation modes:
  • PAM4—Provides up to 12 number of lanes for selection. The IP always instantiates two PCS channels for each lane in PAM4 modulation mode.
  • NRZ—Provides up to 16 number of lanes for selection.
Each modulation mode supports two data modes:
  • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
    Figure 5. Basic Mode Data Transfer
  • Full mode—This is the packet mode data transfer. In this mode, the IP sends a burst and a sync cycle at the start and the end of a packet as delimiters.
    Figure 6. Full Mode Data Transfer